Rejeesh Kutty
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56ddce1e8c
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dmac: create fifo interface to avoid being treated as axi control stream
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2014-05-27 10:25:14 -04:00 |
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Rejeesh Kutty
|
f73819f4d4
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zc706: pl ddr3 initial checkin
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2014-05-13 16:19:53 -04:00 |
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Rejeesh Kutty
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fbfd658f0d
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zc706: added pl ddr3 mig
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2014-04-09 15:58:12 -04:00 |
Istvan Csomortani
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f9a67371c0
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Zynq Base System: Reset is synchronized to lowest system clock
System reset (sys_100m_reset) is synchronized to lowest system
clock (FCLK0), via a Processor System Reset module
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2014-03-26 17:58:14 +02:00 |
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Rejeesh Kutty
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dc44703cf1
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zynq/non-zynq: identical signal names and instances
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2014-03-17 17:02:03 -04:00 |
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Rejeesh Kutty
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a6da4ca01c
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zynq/non-zynq merge variables
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2014-03-17 16:39:52 -04:00 |
|
Rejeesh Kutty
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f3ae57a53e
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global clock and reset names
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2014-03-11 09:57:59 -04:00 |
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Rejeesh Kutty
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ddac1a8834
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added common board files
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2014-02-28 21:17:01 -05:00 |