385ed31a45
make files update
2016-04-29 10:17:35 -04:00
3f5e1e1203
ad9361- dev_if module name change
2016-04-29 10:17:35 -04:00
89f5d2394e
altera- clock variations
2016-04-29 10:17:35 -04:00
243d3e6e41
ad9361- a10soc sdc files
2016-04-29 10:17:35 -04:00
aa2aa902bf
ad9361- a10soc updates
2016-04-29 10:17:35 -04:00
f411d29e30
ad9361- a10soc changes
2016-04-29 10:17:35 -04:00
3563c2212c
common/altera- removed dcfilt/mul
2016-04-29 10:17:35 -04:00
0260280db1
common/altera- data path
2016-04-29 10:17:35 -04:00
ed62101308
common/altera: primitives
2016-04-29 10:17:35 -04:00
779d014750
ad9361-common alt/xil interface
2016-04-29 10:17:35 -04:00
e9b199959a
library/adcfifo- constraints update
2016-04-20 15:57:25 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
d7d8b2cf1c
axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines
2016-04-19 14:38:26 +03:00
e855ef38f4
axi_dacfifo: Initial commit
...
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00
42cd05ab19
ad_mem_asym: Add support for more ratios.
...
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
6fe41ebb08
axi_hdmi_tx: Upgrade hdmi clipping process
...
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
69d721526a
util_dacfifo: Add constraints file
2016-04-12 13:21:50 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
...
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
b31cdac6bd
util_gmii_to_rgmii: Updated to 2015.4
...
The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
2016-03-23 10:14:18 +02:00
46eddd04be
library: port updates on mmcm
2016-03-22 12:50:59 -04:00
de4da6726b
axi_clkgen: port updates on mmcm
2016-03-22 12:50:59 -04:00
74408881c6
axi_ad9122: optional clock out control
2016-03-22 12:50:59 -04:00
65b2e51958
common/mmcm: add another clock
2016-03-22 12:50:59 -04:00
769fecbe00
axi_i2s_adi: Fixed clock association
2016-03-21 20:18:45 +02:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
6d277733d5
axi_spdif_rx: Fixed the clock association
2016-03-18 13:58:13 +02:00
28990e362a
axi_spdif_tx: Fixed the clock association
2016-03-18 13:31:06 +02:00
896c734792
Revert "foobar"
...
This reverts commit a3cb8cac45
2016-03-18 13:23:02 +02:00
a3cb8cac45
foobar
2016-03-18 11:51:13 +02:00
9b2a106aa0
axi_jesd_gt: changed clock and reset naming to be consistent with the other projects
2016-03-15 11:20:31 +02:00
06b7916303
axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:18:25 +02:00
ef05642e26
axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:14:05 +02:00
b3ed38107c
axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:12:45 +02:00
8ecf5edaf8
ad9122- pat modes
2016-03-14 11:14:29 -04:00
31cc91d1b9
adi_ip: Updated to 2014.4.2
...
- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
287770a201
axi_dmac: Fix tlast generation on AXI stream master
...
For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-03-08 10:53:59 +01:00
2524f19ae0
Updated interfaces Makefile and Makefiles for the libraries that depend on it
2016-03-07 12:31:41 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7a320a3d34
ad_lvds* - updates
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
a8e9d72273
adc/dac - prefix parameters
2016-02-17 14:16:04 -05:00
e1c5d6a8f7
axi_ad9684: Fix constraint file
2016-02-12 14:38:59 +02:00
a747fad540
axi_ad9361: tx_valid must be controlled by the TDD controller
2016-02-12 14:33:34 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
0d67af370f
util_upack: Fixed problem when dac valid isn't continuous from the DAC
...
In cases when the dac_valid_ from the DAC is not continuous, in some situations
there were two dac_valid pulses sent to the DMA.
2016-02-04 13:03:46 +02:00
4cc69c0cac
axi_ad9684: Add Makefile
2016-01-19 18:32:11 +02:00
c865dbf353
axi_ad9680: Fix channel instantiation
2016-01-19 12:49:45 +02:00
df3eefdca1
axi_ad9434: Update constraint file
2016-01-19 12:43:05 +02:00
d1e638349b
ad_serdes_clk : The reference clock selection line should by tied to 1
...
Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
c6cfd1a2b6
axi_ad9684: Initial check in
2016-01-19 11:13:45 +02:00
4f2b999999
axi_ad9680: Q_OR_I_N is not used in this channel
2016-01-13 16:26:22 +02:00
838b558176
axi_ad9434: Fix adc_status
...
adc_status was not driven by anything. Should be driven by adc_status_m1.
2016-01-13 12:21:42 +02:00
2dcd9136aa
axi_ad6676: Delete confusing comment
2016-01-13 10:20:18 +02:00
4c2d08a9be
ad9152: altera syntax error
2015-12-11 12:49:00 -05:00
bc93910ee5
ad9152: qsys updates
2015-12-10 16:04:10 -05:00
ff1d98a0c7
ad9144: duplicate include
2015-12-10 16:02:35 -05:00
ce906989d5
ad9152: qsys ip
2015-12-10 09:46:31 -05:00
12c95b059d
ad_tdd_control: Remove tdd_enable_synced control line
...
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
5cf45b2978
axi_clkgen: Added phase related parameters
2015-12-02 18:50:23 +02:00
36febf8591
Merge branch 'master' into dev
...
Conflicts:
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_dmac/Makefile
library/axi_dmac/axi_dmac_constr.ttcl
library/axi_dmac/axi_dmac_ip.tcl
library/common/ad_tdd_control.v
projects/daq2/common/daq2_bd.tcl
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms2/zc706pr/system_project.tcl
projects/fmcomms2/zc706pr/system_top.v
projects/usdrx1/common/usdrx1_bd.tcl
This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
667e49fe41
library: Axi_clkgen, added register for controlling the source clock.
...
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
df58646925
util_adcfifo: Updated altera interface
2015-11-25 10:20:06 +02:00
593c486168
ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received
2015-11-24 15:15:53 +02:00
c70be7391f
ad_tdd_control: Avoid unnecessary reset on control lines
...
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
ee0617661e
axi_ad9680: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:45:12 +02:00
f51871c1e4
axi_ad9144: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:44:07 +02:00
76823f95fa
axi_ad9250: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:39:55 +02:00
275ec3d3a8
axi_ad9361: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:21:08 +02:00
250f3c917b
axi_ad9361: Removed old signals from the altera device interface module
2015-11-24 11:20:35 +02:00
fb269f7a29
util_cpack: Updated altera interfaces
...
- DMA side, simplified naming
- ADC side, added FIFO conduit per channel
2015-11-24 11:18:18 +02:00
e6de2ade78
util_upack: Updated altera interfaces
...
- DMA side, simplified naming
- DAC side, added FIFO conduit per channel
2015-11-24 11:17:02 +02:00
c5ff1674c6
axi_dmac: Updated fifo interfaces for easier connectivity
2015-11-24 11:08:28 +02:00
e5d2f5be06
util_upack: Cosmetic changes
2015-11-24 10:55:10 +02:00
985f2ca020
library: ad_rst, added comment so that the registers are not minimized away
2015-11-24 10:33:38 +02:00
bdf9754971
util_tdd_sync: Sync signals output reg is a false path source
2015-11-17 09:42:05 +02:00
9ba8c059ce
ad_tdd_sync: Fix reset value of the pulse_counter
2015-11-13 18:31:24 +02:00
3c27b3a4c5
ad_lvds_in: Add single ended option
2015-11-13 12:13:09 +02:00
b17fec689e
ad_tdd_control: An active sync pulse can NOT be a reset for the control lines
...
By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
2015-11-11 11:13:33 +02:00
fc0f4bc414
axi_ad9361: Delete the old sync generator from the core
...
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
a290611c09
util_tdd_sync: Initial commit
...
A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 10:46:11 +02:00
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
e7fd964874
axi_clkgen: Added a second input clock option
2015-11-06 17:55:29 +02:00
839e76996f
axi_gpreg: added constraints
2015-11-05 11:28:37 -05:00
482b740229
axi_gpreg: add buffer enable
2015-11-05 11:28:35 -05:00
66d4f8fd58
util_gtlb: output receive/transmit clocks
2015-11-05 11:28:34 -05:00
28bfeb442c
util_gtlb- syntax error fixes
2015-11-05 11:28:31 -05:00
6d28a92b5b
util_adcfifo: Added altera initial constraints file
2015-11-04 13:34:52 +02:00
e8b84b3662
axi_dmac: Updated axis destination / source ports for altera component
2015-11-04 13:33:41 +02:00
de53a61902
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow
...
Added altera component
2015-11-04 13:31:50 +02:00
6cfc13a9dd
common: Allow for the memory to be also symetrical
2015-11-04 13:28:02 +02:00
ad1cef1441
axi_gpreg: compile fixes
2015-11-03 14:29:00 -05:00
c8019b69fd
axi_gpreg- added
2015-11-03 14:28:59 -05:00
88f247a1de
util_gtlb: use gpio
2015-11-03 14:28:57 -05:00
acd9efc528
axi_hdmi_tx: Add parameter to configure the output clock polarity
...
In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
88568c21e1
util_gtlb: updates for latest axi_jesd_gt
2015-10-30 18:47:36 -04:00
2b6ae00a44
library: add mfifo
2015-10-27 14:52:02 -04:00
f1ed27105f
library/common- reset fix
2015-10-23 14:32:35 -04:00
32b3cfd8b9
axi_usb_fx3: Initial commit of the core with interface stub
2015-10-23 13:27:00 +03:00
Rejeesh Kutty
AndreiGrozav
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
István Csomortáni