In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR. The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR. The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Add the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
- allow specifying the name of Axi Lite interface from the peripheral were to connect the control bus
- some DDR controllers have an Axi Lite control interface, this creates
a second address segment which causes issues, differentiate the memory
segment from control registers segment
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.
Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ
Default mode set to:
TX JESD204C MODE 11, M=16, L=4
RX JESD204C MODE 4, M=8, L=2
For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
Occasionally with zed, the implementation failed at the placement stage where
the tool could not fit the logic cells inside a single clock region,
constraint required by the usage of regional clock buffers.
This commit allows the usage of the global clock buffers which help the tool
in such cases and allow a larger application logic to be implemented in fabric.
Fix CONVERTER_RESOLUTION parameter setting for ad9250. Also deleted the
setting of BITS_PER_SAMPLE and DMA_BITS_PER_SAMPLE for ad9250 since they
are set by default to the desired values.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
For CMOS case, lane rates are so low that reference clock of the source
synchronous interface can be routed on non-clock routes. The delays on
the clock line are adjusted by the digital interface tuning controlled
through software.
Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal
placement which causes large skew between clocks at the serdes pins.
1. Reduce max allowed skew between source synchronous clocks that can
occur due PCB differences. 250ps represents a difference more than an
inch.
2. In order to reduce skew between source synchronous clock and the
divided clock instruct the tool to use a common clock root for them.
The default address space for a new bridge is 256 Kbytes. Add an
avl_address_width attribute to the ad_cpu_interoconnect porecess to
define other address space sizes if needed.
The avl_peripheral_mm_bridge will have an 128 Kbyte address space from
address 0x0000.
Laszlo Nagy
LIacob106
Adrian Costina
Filip Gherman
sergiu arpadi
alin724
AndreiGrozav
Dan Hotoleanu
Iulia Moldovan
Stanca Pop
PopPaul2021
Laszlo Nagy
stefan.raus
Robin Getz
hotoleanudan
Istvan Csomortani
Mihaita Nagy