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1161 Commits (5a309d8863aa64bdab2463d9c4243872a1965801)

Author SHA1 Message Date
Rejeesh Kutty 5a309d8863 avl_adxphy- split 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 2a34f9baa8 alt-serdes, in & out 2016-09-12 11:45:23 -04:00
Rejeesh Kutty 9e0c39a71b alt_serdes_clk- changes 2016-09-12 10:30:28 -04:00
Istvan Csomortani f4be0524b4 altera/common: Add SERDES related modules 2016-09-09 18:04:41 +03:00
Istvan Csomortani a183e51a12 axi_ad9361: Add parameter R1_MODE_EN 
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
 2016-09-09 16:34:11 +03:00
Istvan Csomortani e42206e510 axi_ad9361: Add a TDD enable/disable parameter 2016-09-09 14:38:28 +03:00
Istvan Csomortani be41a8bcaa axi_ad9361: Delete debug ports of the tdd module 2016-09-09 14:38:28 +03:00
AndreiGrozav bbcf2a3ec3 axi_ad9434/axi_ad9434_constr: Change constraint file to resolve critical warning 2016-09-01 17:16:59 +03:00
Rejeesh Kutty 4ae084ee32 avl_adxcvr- compile fixes 2016-09-01 10:06:28 -04:00
Rejeesh Kutty 5544e3cf10 axi_adxcvr- compile fixes 2016-09-01 10:06:28 -04:00
Rejeesh Kutty 230f1526c0 avl_adxcfg- compile fixes 2016-09-01 10:06:28 -04:00
Rejeesh Kutty b7ea2efa87 altera- xcvr cores 2016-08-29 15:18:48 -04:00
Rejeesh Kutty 9799599eee library/ad9361- add dac clk sel 2016-08-26 10:31:00 -04:00
Rejeesh Kutty 74bc498a6d library/common- added dac clock select 2016-08-26 10:31:00 -04:00
Shrutika Redkar 10b9a0e52f upadated xcvr ips 2016-08-17 15:51:55 -04:00
Adrian Costina 6a8ca8107a common: Added common ad_dcfilter stub for altera. 2016-08-16 17:37:16 +03:00
Rejeesh Kutty e754f0a46a up_axi- writes dropped by delayed w-responses 2016-08-14 11:21:19 -04:00
Rejeesh Kutty 3427965cd2 adxcvr- add u-gth bufg 2016-08-11 10:00:41 -04:00
Rejeesh Kutty bb9cb86f34 adc/dac- fifo constraints 2016-08-11 10:00:41 -04:00
Shrutika Redkar 829e4155ca modified transceiver configuration files 2016-08-10 14:59:38 -04:00
Shrutika Redkar b8f4e1c0aa updated 9680 hdl files(to resolve a critical warning) 2016-08-10 14:50:31 -04:00
Istvan Csomortani ccf1c56b33 util_upack: Patch up the description of Altera IP 2016-08-08 16:39:56 +03:00
Istvan Csomortani e9ac4a5a0e util_rfifo: Patch up the description of Altera IP 2016-08-08 16:39:25 +03:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani aad8c265bc lib_refactoring: Fix path for CMOS sources 2016-08-08 15:07:54 +03:00
Istvan Csomortani 1d33d7d7ee lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common 2016-08-08 15:07:42 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Istvan Csomortani 90ac7b7ac9 lib_refactoring: Move all Altera module to library/altera/common 
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
 2016-08-08 15:07:01 +03:00
Istvan Csomortani cb9af99c5d lib_refactoring: Add ad_mul.v for Altera 2016-08-08 15:06:48 +03:00
Istvan Csomortani b806fa3b42 lib_refactoring: Move all the Xilinx common modules to library/xilinx/common 2016-08-08 15:06:10 +03:00
Adrian Costina 5faf4c4976 cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them 2016-08-05 16:27:52 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty cb23ba8bb7 make- script needs update 2016-08-04 14:17:04 -04:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Rejeesh Kutty 2b7c976be5 xcvr- altera/xilinx split 2016-08-04 13:26:10 -04:00
Lars-Peter Clausen cba53774ca axi_dmac: Don't add CDC constraints when all clocks are synchronous 
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-08-02 19:30:24 +02:00
Adrian Costina aece3f5555 axi_ad9680: Update IP core 
- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
 2016-08-01 15:05:30 +03:00
Istvan Csomortani a0ae791395 hdl-vivado-2016.2: Update axi_jesd_gt 
Infer AXI bus interfaces separately.
 2016-08-01 13:53:18 +03:00
Istvan Csomortani fbe3d75eb0 cosmetics: Delete trailing whitespace characters 2016-08-01 13:46:46 +03:00
Matthew Fornero b99117e686 up_axi: Same cycle BVALID/READY fails on Altera 
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
 2016-08-01 12:17:10 +03:00
Istvan Csomortani 58b220ba81 ad_tdd_control: Add an on/off switch to the receive datapath 
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
 2016-08-01 11:49:27 +03:00
Rejeesh Kutty 7988d2c7a2 adi_ip: remove duplicated errored auto address maps & interfaces 2016-07-29 12:32:19 -04:00
Shrutika Redkar 4aa506de8d adxcvr- added a space? 2016-07-29 09:38:08 -04:00
Shrutika Redkar 71dad14e0e axi_adcfifo- disable auto infer mess-up 2016-07-29 09:37:17 -04:00
Shrutika Redkar 39ff059ef6 hdl-vivado-2016.2- productivity decimated again! 2016-07-28 13:44:57 -04:00
Shrutika Redkar d5d61ff518 hdl-vivado-2016.2- productivity decimated again! 2016-07-28 13:44:57 -04:00
Shrutika Redkar 52b544bb66 hdl-vivado-2016.2- auto infer bus interfaces 2016-07-28 13:44:57 -04:00
Shrutika Redkar 3384d384d3 hdl-vivado-2016.2- infer bus interfaces separately 2016-07-28 13:44:57 -04:00
Shrutika Redkar c316f0dfea ad9144- synthesis warnings fix 2016-07-28 13:44:57 -04:00
Shrutika Redkar 8a2734b43e up_dac_common- typo- unf register reset 2016-07-28 13:44:57 -04:00