1db04a47b8
ad9083_evb: Update parameters to 10Gpbs lane rate
2021-04-19 13:21:34 +03:00
8335e1bd9a
sysid: Make sure gitbranch_string is always declared
...
Parsing of not existed "gitbranch_string" fails the build process.
2021-03-24 13:34:32 +02:00
6a374ef457
ad469x/zed: Add multicycle path constraint
2021-03-22 13:05:05 +02:00
40baa63f0f
adrv2crr_fmcomms8: Fix system_top.v
2021-03-19 17:56:28 +02:00
a1773c661c
adrv9009zu11eg_crr: Update spi
...
Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
3dce87d09b
ad9083: Add reference design for ad9083 eval board
2021-03-10 10:52:03 +02:00
dcec4fe1b7
adrv9001/zc706: Fix spaces
2021-03-10 10:35:52 +02:00
dc186645d8
adrv9001/zc706: Fix comments HPC to LPC
2021-03-10 10:35:52 +02:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
...
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
1099badaf4
ad9082_fmca_ebz:zc706: Initial version
2021-03-05 15:54:23 +02:00
2213527f29
ad9082_fmca_ebz:zcu102: Initial version
2021-03-05 15:54:23 +02:00
f56e3c305b
ad9082_fmca_ebz:vcu118: Initial version
2021-03-05 15:54:23 +02:00
6b13b32f24
ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
2021-03-04 11:13:29 +02:00
677c154134
adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
...
Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
2021-03-04 11:13:10 +02:00
03de08609b
fmcomms2/zed: Disable unused TDD to save space and timing
2021-03-04 11:13:10 +02:00
0dd3173547
adrv9001/zc706: Initial commit
...
The project supports CMOS interface only.
VADJ on the ZC706 must be programmed to 1.8V
Instructions can be found here:
https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086
2021-03-03 09:03:03 +02:00
3be5137aec
cn0540/cora: Remove multicycle constraint
...
Design uses 80MHz spi_clk which does not require
special considerations
2021-02-18 14:14:16 +02:00
701e5f6515
scripts/adi_board.tcl: Add simulation support
...
This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
2021-02-12 16:21:10 +02:00
0374a7c1ac
ad9081_fmca_ebz/vcu118: Added common 204C use cases as example
2021-02-05 15:24:15 +02:00
ddd8a14790
ad9081_fmca_ebz: Remove system reset from Xilinx PHY
...
Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
2021-02-05 15:24:15 +02:00
af3e1c7003
ad9081_fmca_ebz/a10soc: Np 12 support
2021-02-05 15:24:15 +02:00
f73ed741c9
fmcadc5: Connect link clock to second JESD link layer
2021-02-05 15:24:15 +02:00
3f2f88ebbc
ad_fmclidar1_ebz: Set bits per sample towards the DMA interface
2021-02-05 15:24:15 +02:00
dafdd1c1e9
ad9208_dual_ebz: Use ad_xcvrcon procedure to connect device clock
2021-02-05 15:24:15 +02:00
bb9eafceef
ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency
2021-02-05 15:24:15 +02:00
d0f8a81b2f
ad9081_fmca_ebz: Np 12 support
...
204B functional
204C functional
2021-02-05 15:24:15 +02:00
454b900f90
jesd204: Xilinx: NP=12 support
...
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
2021-02-05 15:24:15 +02:00
7be66b63c1
adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8
2021-02-05 15:07:09 +02:00
6d504d14cf
fmcomms8: zcu102: Fix lane swapping
2021-02-05 15:07:09 +02:00
0fd5590e56
ad9081_fmca_ebz: a10soc: Initial version
...
Parametrizable project with default profile of:
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
6e6c51dd27
common/a10soc: Bridge support
2021-02-05 10:24:59 +02:00
f0b753321a
common/intel: Add util_adcfifo integration script
2021-02-05 10:24:59 +02:00
3041e77659
ad40xx/zed: Update constraints
2021-02-04 11:04:32 +02:00
05469a011c
ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA
2021-02-04 11:04:32 +02:00
dd4c8d6807
adrv9001/zcu102: Add debug header
2021-01-26 15:22:41 +02:00
728904af09
adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing
2021-01-26 15:22:41 +02:00
bae7e48c50
adrv9001/common: Run DMAs @ 100MHz
2021-01-26 15:22:41 +02:00
f68c222489
cn0501/coraz7s: Fix sysid
2021-01-22 15:40:37 +02:00
bb44e5399f
adrv9001/zed: Connect TDD sync to PMOD JA1
2021-01-20 13:00:01 +02:00
3918d43cd1
adrv9001/zcu102: Add TDD sync to PMOD0 J55.1
2021-01-20 13:00:01 +02:00
fe9f72db9c
adrv9001/common: Export TDD mode signal
2021-01-20 13:00:01 +02:00
18b2a8b0a7
adrv9001/zed: Add TDD support
2021-01-20 13:00:01 +02:00
0c2745361b
adrv9001/zcu102: Add TDD support
2021-01-20 13:00:01 +02:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
da61515d41
ad40xx: Fix bd.tcl script
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
...
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
da9828a63e
ad9081:zcu102: Expose parameters to environment
...
Allow setting project parameters from the environment.
2021-01-19 17:10:08 +02:00
235fb4859a
usrpe31x: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
f1421c91ee
sidekiqz2: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
f68393ecb9
adrv936x: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
3e237459e3
pluto: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
d9639db991
m2k: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
e41ba7f6f5
adrv9009zu11eg: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
9ec3408c79
adi_project_xilinx: Fix the adi_project process
...
In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.
NOTE: In these case we should use adi_project_create directly in system_project.tcl.
2021-01-15 15:26:43 +02:00
b9ac8df503
project-xilinx.mk: Add *.hbs to clean list
2021-01-15 13:50:53 +02:00
067b57d404
vc707: Fix mdio intf
2021-01-15 13:50:53 +02:00
c54552d823
adi_project_xilinx: Add env var
...
add ADI_DISABLE_MESSAGE_SUPPRESION which disables
adi_xilinx_msg.tcl
projects/scripts/adi_project_xilinx.tcl
2021-01-15 13:50:53 +02:00
ead4513ad6
adi_xilinx_msg: Downgrade Synth 8-2490
2021-01-15 13:50:53 +02:00
51b5e4f58b
tcl: Change Vivado version to 2020.1
...
handoff is now exported as .xsa
2021-01-15 13:50:53 +02:00
fbb2a0e1a0
de10nano: Add hps_conv_usb_n signal to stabilize UART lines
...
Without defining this signal, the UART lines receive garbage data
when no cable is connected to the J4 USB UART port.
The GPIO9 is enabled in the reference base design along with the
4MA CURRENT_STRENGTH constraint on the UART pins
2021-01-13 15:36:45 +02:00
dee108ba22
fmcomms8/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
85f5dc8230
ad9371x/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
d539a8119c
adrv9009/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
bab3426f91
scripts: allow directly specifying a device when creating a project
...
Add a layer under adi_project that allows you to directly specify a device/board combination without determining it from the project name.
2021-01-12 14:13:07 +02:00
b989ba36d1
axi_spi_engine: Fix util_axis_fifo instance related issues
2021-01-08 12:29:26 +02:00
5c87e5b1a7
cn0501: Initial commit for Coraz7s
2020-12-18 14:05:56 +02:00
71009e74ff
ad7768_if: Remove buffers, add parallel data path
2020-12-15 15:16:14 +02:00
fa67eb5532
adv7513_de10nano: Fix gpio_bd assignments
2020-12-08 14:38:04 +02:00
e331abedc6
common/de10nano: Cosmetic updates only
2020-12-08 14:38:04 +02:00
8d378c56bf
common/de10nano: Full HD 60 FPS support
...
-change the video memory interfacing from f2h_axi_slave to
f2h_sdram0
- add f2h_sdram1 port as the default interface for converter DMA
- set as default the full HD resolution at 60 FPS (pixel clock 148.5MHz)
- use a second 200MHz(198MHz) clock from the pixel_clk_pll, as DMA source
to destination clock.
2020-12-08 14:38:04 +02:00
3dd370a27c
ad9081_fmca_ebz: enable xbar in DAC TPL
2020-11-27 09:45:11 +02:00
ad755788a0
ad9081_fmca_ebz/zc706: Initial version
...
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2020-11-12 15:46:27 +02:00
e9f319e3d7
ad9081_fmca_ebz: HP0 is already initialized in ZC706
...
On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
2020-11-12 15:46:27 +02:00
b080b52a14
daq3:zcu102: Connect overflow pins for the AD9680 TPL
2020-11-11 14:24:02 +02:00
2799777657
adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections
2020-11-11 07:07:29 -05:00
ecd880d44c
adrv9009zu11eg:fmcomms8: Fix SPI timing constraint
2020-11-05 17:42:41 +02:00
685ca91f19
ad_fmclidar1_ebz/a10soc: Fix a typo
...
Fixing a typo in projects/ad_fmclidar1_ebz/a10soc/system_top.v.
2020-11-05 12:53:50 +02:00
2ff5420630
Update system_top.v
...
Add a comment that the spi CS decoding is tied to a setting in the device tree.
2020-11-02 16:59:08 +02:00
78b2ae02a1
ad9434_fmc,ad9467_fmc,fmcadc5: Update projects to use ad_iobuf, not IOBUF
2020-11-02 16:13:35 +02:00
a3a610728c
intel: Update projects to use ad_iobuf instead of ALT_IOBUF
2020-11-02 16:13:35 +02:00
ae7ec82334
adrv9009zu11eg: Update spi module to use generic verilog
2020-11-02 16:13:35 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
...
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
912e09ad18
m2k: Add DAC last sample connections
2020-11-02 15:50:12 +02:00
d676cfd64f
adv7513/de10nano: Define the USB clock
2020-10-30 10:55:01 +02:00
c048a9243a
de10nano: Fix IO assignments
...
- define IO assignments for HPS SPI master
- delete unused GPIO ports
2020-10-30 10:55:01 +02:00
7cc5716ea8
ad469x: Remove sysid custom string init
2020-10-28 11:31:50 +02:00
5359d991b2
ad469x_zed: Update bd.tcl with new port names
2020-10-28 11:31:50 +02:00
ad4adddbe5
ad469x_fmc: Minor cosmetic update on the config file
2020-10-27 10:09:50 +02:00
0644edb389
fmcomms8: a10soc: Move RX and Observation to second SDRAM interface
...
This is an attempt to get full bandwidth without a FIFO
2020-10-26 18:12:14 +02:00
3a5097875f
common: a10soc: Allow for the second SDRAM interface to be used at a different clock
2020-10-26 18:12:14 +02:00
6621fbec61
fmcomms8: a10soc: Initial commit
2020-10-26 18:12:14 +02:00
35e4eb6a7b
ad469x: Add reference design for ad469x eval board
2020-10-22 19:17:10 +03:00
83cebe899f
daq3: Update projects to the new TPL
...
Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
2020-10-21 18:59:37 +03:00
9f58b465ea
adaq7980: Add AXI pulse generator to generate the offload trigger
2020-10-21 09:59:26 +03:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
1f6bba0aa1
ad77681: Add axi_clkgen ip for spi engine
...
spi_clk changed from 40MHz to 80MHz
2020-10-19 10:42:21 +03:00
d6b23d5149
scripts/adi_pd_intel: Delete noisy print outs
2020-10-17 08:02:33 +03:00
66672932d5
adv7513/de10nano: Fix connection of ltc2308 SPI's interface
2020-10-14 10:37:14 +03:00
72635d73e3
cn0540: Add axi_clkgen to Makefile
2020-10-14 00:05:57 +03:00
9364c8501a
adrv9009_zu11eg: Add synchronization at application layer
...
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
Laszlo Nagy
vladimirnesterov
Sergiu Arpadi
stefan.raus
Adrian Costina
Istvan Csomortani
aholtzma
AndreiGrozav
IMoldovan