Commit Graph

5763 Commits (589cfc6b1b1850133c5812df36f37be63ddf7895)

Author SHA1 Message Date
Laszlo Nagy 589cfc6b1b jesd204_tx_static_config: Update to Np 12 interface changes 2021-02-05 15:24:15 +02:00
Laszlo Nagy 93897b4cb5 jesd204_rx_static_config: Update to Np 12 interface changes 2021-02-05 15:24:15 +02:00
Laszlo Nagy 71475e7dd8 jesd204: Expose core synthesis parameters through registers
Make synthesis parameters accessible for the drivers.
Rework implementation to reflect the parameters of the actual core and
not of the AXI interfacing core.
2021-02-05 15:24:15 +02:00
Laszlo Nagy 454b900f90 jesd204: Xilinx: NP=12 support
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.

e.g  Input datapath width = 4; Output datpath width = 6;
  for F=3 one beat contains 2 frames
  for F=6 one beat contains 1 frame

The width change is realized with a gearbox.

Due the interface width change the single clock domain core is split
in two clock domains.
  - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
  -              lane rate / 20 for input datapath width of 8 octets 8b10b
  -              lane rate / 66 for input datapath width of 8 octets 64b66b

  - Device clock : Link clock * input data path width / output datapath width

Interface to transport layer and SYSREF handling is moved to device clock domain.

The configuration interface reflects the dual clock domain.

If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
2021-02-05 15:24:15 +02:00
Laszlo Nagy e909962fb0 common/ad_upack: Generic unpacker core and testbench
Unpacker:
   - unpack O_W number of data units from I_W number of data units
   - data unit defined in bits by UNIT_W e.g 8 is a byte
2021-02-05 15:24:15 +02:00
Laszlo Nagy b4ebd4357f common/ad_pack: Generic packer core and testbench
Packer:
   - pack I_W number of data units into O_W number of data units
   - data unit defined in bits by UNIT_W e.g 8 is a byte
2021-02-05 15:24:15 +02:00
Laszlo Nagy 6ef803e7ab jesd204: Make character replacement opt in feature
In order to keep resource utilization low and for better timing closure
allow disabling of the character replacement logic.

If the parameter is set the frame alignment monitoring is limited to links
where scrambling is on.
2021-02-05 15:24:15 +02:00
Matt Blanton 7093e10ebf jesd204: Fixed TX frame mark timing. Added start and end of multiframe signals as RX and TX ports 2021-02-05 15:24:15 +02:00
Matt Blanton 400c3927f7 jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode,
and frame alignment character replace/insert with or without scrambling.
Add support for xcelium simulator to jesd204/tb
Increased cores minor version.
2021-02-05 15:24:15 +02:00
Adrian Costina 7be66b63c1 adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8 2021-02-05 15:07:09 +02:00
Adrian Costina 6d504d14cf fmcomms8: zcu102: Fix lane swapping 2021-02-05 15:07:09 +02:00
Istvan Csomortani 769b195800 util_axis_fifo: Add support for tlast 2021-02-05 13:35:06 +02:00
Laszlo Nagy 0fd5590e56 ad9081_fmca_ebz: a10soc: Initial version
Parametrizable project with default profile of:

  M=8 L=4 SampleRate=250 MSPS
  LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
Laszlo Nagy 6e6c51dd27 common/a10soc: Bridge support 2021-02-05 10:24:59 +02:00
Istvan Csomortani f0b753321a common/intel: Add util_adcfifo integration script 2021-02-05 10:24:59 +02:00
Istvan Csomortani 3041e77659 ad40xx/zed: Update constraints 2021-02-04 11:04:32 +02:00
Istvan Csomortani 05469a011c ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA 2021-02-04 11:04:32 +02:00
Istvan Csomortani 93f46ef6e3 spi_engine_execution: Add constraints file 2021-02-04 11:04:32 +02:00
Istvan Csomortani ab10bd136e spi_engine_execution: Add echoed SCLK support
There are boards (e.g. AD4630-24) which take the SCLK and echo back to
the FPGA through a level shifter - doing this removes the effect of
round-trip timing delays from the level shifter. This is commonly done
whenever isolators are used since they are very slow.

By setting the ECHO_SCLK parameter to 1, the IP will use the incoming
echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still
synchronous to the SPI clock, and it's generated after the last valid
SDI latch.

The designer's responsibility is to time the SDI shift registers in order to
respect the design requirements.
2021-02-04 11:04:32 +02:00
Laszlo Nagy 6f4053f3b0 util_adxcvr: Fix PRBS synchroniser typo
The control lines for TX PRBS must be synchronized using the TX clock.
2021-01-29 14:01:25 +02:00
Laszlo Nagy dd4c8d6807 adrv9001/zcu102: Add debug header 2021-01-26 15:22:41 +02:00
Laszlo Nagy 728904af09 adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing 2021-01-26 15:22:41 +02:00
Laszlo Nagy bae7e48c50 adrv9001/common: Run DMAs @ 100MHz 2021-01-26 15:22:41 +02:00
Laszlo Nagy 714d557245 axi_adrv9001: Add opt-in synthesis parameters 2021-01-26 15:22:41 +02:00
Laszlo Nagy 31929167d3 axi_adrv9001: Use global clocks for divided down clock 2021-01-26 15:22:41 +02:00
Laszlo Nagy 8476993c1b ad_pnmon: Fix zero checking when valid not constant 2021-01-26 15:22:41 +02:00
Laszlo Nagy c7046a6d72 axi_adrv9001:axi_adrv9001_rx_channel: fix ramp signal checking 2021-01-26 15:22:41 +02:00
Sergiu Arpadi f68c222489 cn0501/coraz7s: Fix sysid 2021-01-22 15:40:37 +02:00
Laszlo Nagy 669217db8b ad_tdd_control: Avoid single pulses if tx_only or rx_only 2021-01-20 13:00:01 +02:00
Laszlo Nagy 843c2565f7 up_tdd_cntrl: Split large synchronizer in smaller ones
This will help placement.
2021-01-20 13:00:01 +02:00
Laszlo Nagy 54c2cf7d12 ad_tdd_control: Fix rx/tx only behavior
When tx_only disable rx_enable and vice-versa
2021-01-20 13:00:01 +02:00
Laszlo Nagy bb44e5399f adrv9001/zed: Connect TDD sync to PMOD JA1 2021-01-20 13:00:01 +02:00
Laszlo Nagy a47cc59c67 common/up_tdd_cntrl: Fix read data when read is idle 2021-01-20 13:00:01 +02:00
Laszlo Nagy 3918d43cd1 adrv9001/zcu102: Add TDD sync to PMOD0 J55.1 2021-01-20 13:00:01 +02:00
Laszlo Nagy fe9f72db9c adrv9001/common: Export TDD mode signal 2021-01-20 13:00:01 +02:00
Laszlo Nagy 58f2eec127 axi_adrv9001: Export TDD mode 2021-01-20 13:00:01 +02:00
Laszlo Nagy 18b2a8b0a7 adrv9001/zed: Add TDD support 2021-01-20 13:00:01 +02:00
Laszlo Nagy 0c2745361b adrv9001/zcu102: Add TDD support 2021-01-20 13:00:01 +02:00
Laszlo Nagy afa3f11206 axi_adrv9001: Add TDD support 2021-01-20 13:00:01 +02:00
Laszlo Nagy 7e63113734 library/common/up_tdd_cntrl: Make address generic 2021-01-20 13:00:01 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
Sergiu Arpadi da61515d41 ad40xx: Fix bd.tcl script 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Laszlo Nagy da9828a63e ad9081:zcu102: Expose parameters to environment
Allow setting project parameters from the environment.
2021-01-19 17:10:08 +02:00
Istvan Csomortani d82f61b9af util_axis_fifo: Add KEEP synthesis attribute for zerodeep CDC
Vivado synthesis is optimizing out the zerodeep block, resulting untreated
clock domain crossing. Set KEEP attribute for the registers.
2021-01-19 14:28:07 +02:00
Istvan Csomortani 235fb4859a usrpe31x: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani f1421c91ee sidekiqz2: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani f68393ecb9 adrv936x: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani 3e237459e3 pluto: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani d9639db991 m2k: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00