Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Corrected the ADC/DAC interrupt location for microblaze systems
Removed the ILA clock generation from sys_audio_clkgen and created a
separate clock generator
All system is reset from the same source
The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data
path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO.
The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16
period so the constraints were modified accordingly.
Adrian Costina
Rejeesh Kutty
Lars-Peter Clausen