c215eab696
ad9122: register map updates
2014-07-30 11:32:15 -04:00
b97bdcdc23
ad9122: register map updates
2014-07-30 11:32:13 -04:00
a2b728b91e
util_adc_pack: added extra registers to meet timing.
...
Util_dac_unpack: fixed issue regarding changing from 1 channel to 2
2014-07-25 17:41:47 +03:00
26a019ae6e
util_adc_pack: Fixed issue regarding changing from 1 channel to 2
2014-07-25 10:20:49 +03:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
6346017763
c5soc: changed to alt_lvds - 250M is too high for cyclone v
2014-07-24 20:51:40 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
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The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
701dc96016
up_dac_channel: make iq cor coeff(s) tc
2014-07-24 10:10:24 -04:00
191f994e79
prcfg: Fixed the PRBS lock issue on BIST
2014-07-24 09:41:13 +03:00
db1c931736
ad9625_plddr: PL DDR3 fixes
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- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
4da8100fe5
ad9625_plddr: Delete trailing whitespaces.
2014-07-23 19:31:07 +03:00
54b2cd74bf
motor_control: cores modified so they can compile with the new common files
2014-07-23 11:58:50 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
a9992f02b0
fifo2s: bug fixes- on 64mhz dma clock
2014-07-08 16:57:44 -04:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
dc78ced443
prcfg_lib: Change the prcfg_top interface
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Use the device core's gpio_input and gpio_output registers to get/set
status and control of PR.
2014-07-08 12:28:25 +03:00
75e624ef15
prcfg_lib: Flop the status and mode nets
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Flop the status and mode nets in case of BIST and QPSK configurations.
2014-07-08 12:23:48 +03:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
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Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
f3b20fd148
axi_ad9625: register map updates
2014-07-03 11:19:31 -04:00
1a78ac453e
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-07-02 15:39:42 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
e4ce00f7fb
axi_ad9680: register map changes
2014-07-02 12:50:09 -04:00
7e5748374d
prcfg_lib: Fixed prbs generator for QPSK
2014-07-02 18:14:35 +03:00
8eb7a55797
prcfg_lib: Fixed the gpio status merge logic
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The previous logic did not passed implementation.
2014-07-02 18:09:48 +03:00
9089877c70
prcfg_lib: Fixed the sine tone generator for BIST
2014-07-02 18:00:43 +03:00
8a2b29cdbe
axi_damc: Add xfer_req to the FIFO source interface
...
The xfer_req signal will be high if DMA core the is expecting data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-07-02 16:05:16 +02:00
31abd07613
axi_ad9144: register map changes
2014-07-01 21:43:04 -04:00
60dd14bcdb
a5soc: removed jtag master control
2014-07-01 12:27:37 -04:00
b6052773b7
added adc/dac gpio registers
2014-06-27 14:45:58 -04:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
4afe6c24e9
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-06-25 15:26:21 -04:00
10a7804e14
ad9361: altera wrapper updates
2014-06-25 15:26:06 -04:00
4fdb3cfc4a
ad9250: register map updates
2014-06-25 15:23:57 -04:00
4f5d163fcc
Merge branch 'master' into devel
2014-06-25 13:07:12 -04:00
e38813fa9f
fifo- monitor status signals
2014-06-25 12:15:13 -04:00
4877df9bec
axi_fifo2s: make read dead slow
2014-06-25 09:20:57 -04:00
985ace533e
ad9361: remove unused modules
2014-06-24 14:26:40 -04:00
6b3312bbf9
library: register map changes and for mathworks
2014-06-24 14:24:22 -04:00
d4be46cc17
library: register map changes and for mathworks
2014-06-24 14:23:56 -04:00
e650253013
library: register map changes and for mathworks
2014-06-24 14:22:05 -04:00
89961c8dd7
prcfg_lib: Update the PR libraries
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+ Flop the control nets too inside the adc/dac module
+ Flop the gpio_out in prcfg_top
2014-06-13 20:35:35 +03:00
7efd6149f8
daq2: initial checkin
2014-06-12 15:54:25 -04:00
87bec07a22
ad9625: added multi-sync support
2014-06-12 15:45:34 -04:00
5189d200e7
axi_fifo2s: linux fix on interfaces
2014-06-12 15:30:13 -04:00
3e5990366e
axi_ad9625: initial release
2014-06-09 16:39:08 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
ea22d29862
prcfg: Initial check in of PR modules
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Initial check in of the partial reconfiguraiton modules.
2014-06-05 14:58:14 +03:00
5b5bca400f
ad9361: added adc loopback
2014-05-27 14:47:59 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
56ddce1e8c
dmac: create fifo interface to avoid being treated as axi control stream
2014-05-27 10:25:14 -04:00
0cd43e34f5
dds: zero scale fix
2014-05-21 11:54:49 -04:00
916afd460f
axi_jesd_gt: synchronization support
2014-05-19 14:17:31 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
a007add714
iqcorrection: missing input signals fix
2014-05-09 11:17:50 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
1d50489870
ad9361: ml605 updates
2014-05-05 11:03:57 -04:00
5f2fb45b24
library: ported hdmi tx to altera
2014-05-02 12:07:47 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
02e8b27626
initial checkin-9250 copy
2014-04-28 21:31:16 -04:00
01de117b5f
motor_control: Changed controller to PID controller. Some estetic changes
2014-04-28 17:57:51 +03:00
fa998a406b
dma: parameter fix
2014-04-24 15:50:16 -04:00
314ec3d343
altera-9250/dma: make id width generic
2014-04-24 14:54:19 -04:00
dfc2bba335
ad9671: updates to allow default adc setup routines
2014-04-23 16:39:28 -04:00
213e852e11
motor_control: Initial commit
2014-04-18 18:57:18 +03:00
503096de18
gt: change userready on drp clock
2014-04-17 16:09:55 -04:00
570ec26798
FMCOMMS2: Added sync option
2014-04-11 18:14:48 +03:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
...
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
af07f8874f
wfifo/rfifo: asynchronous interface
2014-04-10 14:01:40 -04:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
dc7b3e085c
axi_dmac: Fix issues with non 64-bit AXI masters
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Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
36ef882da0
axi_dmac: data_mover: Improve timing
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We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.
Also simplify a few expressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:06:44 +02:00
090d3aee04
axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
cb630e36a9
axi_dmac: src_fifo_inf: Simplify data path
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Improves timing a bit
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
f9ca4fb8be
axi_fifo: Slightly improve timing
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It is OK to overwrite invalid data with other invalid data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
4c9647f289
axi_dmac: axi_register_slice: Provide default values for registers
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
fa5ba6c09d
axi_dmac: Make cyclic mode runtime configurable
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
7ca43f4920
axi_dmac: address_generator: Make 'len' registered
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Slightly improves the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
66e6c1cc21
axi_dmac: axi_register_slice: Remove reset "latch" from datapath
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Move the datapath updates out of the else branch of the reset condition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
799d2384d8
up_xfer_cntrl: Remove extra semicolon
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
9d19145713
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-10 10:50:53 +03:00
5aac9d7288
FMCOMMS2 added sync option
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Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
e73952a694
ad9467 : initial checkin
2014-04-09 17:34:40 +03:00
8bebc5e3d4
ad9671: initial checkin
2014-04-07 13:01:10 -04:00
f8f2684b7e
up_gt: eyescan delay bug fix
2014-04-02 16:45:41 -04:00
e85153b5dd
altera hal version
2014-04-01 21:12:11 -04:00
80e5051894
axi_jesd_gt: initial checkin
2014-04-01 15:14:28 -04:00
2472d61daf
ad_gt_es: status asserted early for latency
2014-04-01 15:06:51 -04:00
0d678b89ed
altera a5gt fmcjesdadc1 setup
2014-04-01 11:46:37 -04:00
724bd70a06
altera additions and replacements
2014-04-01 11:18:10 -04:00
25f416e46f
dds output is reset if disabled
2014-03-31 10:01:49 -04:00
d3d26e1220
lower the address space requirements
2014-03-26 11:03:45 -04:00
9b4539b7c2
axi_dmac: Add option to configure the FIFO size
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-26 12:51:35 +01:00
ca7a70650d
axi_dmac: Delay up_ack by one clock cycle
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The read data also becomes available only with a delay of one clock cycle,
sending the ack too early will result in bogus register reads.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-25 14:35:52 +01:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
ATofan
U-ANALOG\ACostina
Istvan Csomortani