zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
4,903 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

19 Commits (57f83f86aba30b3ad5b7d02b637b6d4e80d32bc0)

Author SHA1 Message Date
Lars-Peter Clausen b19d09e678 axi_ad9680: Use the generic JESD204 ADC receiver core 
Replace the axi_ad9680 implementation with the new generic JESD204
interface ADC core. The replacement is functionally equivalent.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Lars-Peter Clausen 324da5f112 Remove unused DMA underflow signal from ADC DMA interface 
The ADC DMA will never underflow and unsurprisingly the adc_dunf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP 
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
 2018-04-11 15:09:54 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints 
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
 2017-03-30 16:16:02 +03:00
Shrutika Redkar b8f4e1c0aa updated 9680 hdl files(to resolve a critical warning) 2016-08-10 14:50:31 -04:00
Rejeesh Kutty 5c91e41da8 ad9680- sof + sample delineation 2016-07-21 16:09:33 -04:00
Istvan Csomortani 7b858bc5ad Revert commit 6b99ce 
Revert 6b99ce2482
 2015-08-26 13:48:28 +03:00
Adrian Costina 6b99ce2482 library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2 2015-08-20 18:17:38 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Rejeesh Kutty e2f4a4c5cf library: make preset registered for timing paths 2015-06-10 13:41:41 -04:00
Adrian Costina 8a1f4bf5f6 ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports 2015-06-09 14:21:12 +03:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Rejeesh Kutty 4fb1be0672 ad9680: delay changes 2015-05-19 12:53:56 -04:00
Adrian Costina 97dc7ea004 axi_ad9680: Added CDC and reset constraints 2015-04-23 10:40:41 +03:00
Rejeesh Kutty 88a3b7f8fd library: remove all constraints for now 2014-10-07 16:59:19 -04:00
Rejeesh Kutty 1396a215e5 library: local constraints 2014-08-14 15:09:47 -04:00
Rejeesh Kutty e4ce00f7fb axi_ad9680: register map changes 2014-07-02 12:50:09 -04:00
Rejeesh Kutty 7efd6149f8 daq2: initial checkin 2014-06-12 15:54:25 -04:00