4877df9bec
axi_fifo2s: make read dead slow
2014-06-25 09:20:57 -04:00
89961c8dd7
prcfg_lib: Update the PR libraries
...
+ Flop the control nets too inside the adc/dac module
+ Flop the gpio_out in prcfg_top
2014-06-13 20:35:35 +03:00
7efd6149f8
daq2: initial checkin
2014-06-12 15:54:25 -04:00
87bec07a22
ad9625: added multi-sync support
2014-06-12 15:45:34 -04:00
5189d200e7
axi_fifo2s: linux fix on interfaces
2014-06-12 15:30:13 -04:00
3e5990366e
axi_ad9625: initial release
2014-06-09 16:39:08 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
ea22d29862
prcfg: Initial check in of PR modules
...
Initial check in of the partial reconfiguraiton modules.
2014-06-05 14:58:14 +03:00
5b5bca400f
ad9361: added adc loopback
2014-05-27 14:47:59 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
56ddce1e8c
dmac: create fifo interface to avoid being treated as axi control stream
2014-05-27 10:25:14 -04:00
0cd43e34f5
dds: zero scale fix
2014-05-21 11:54:49 -04:00
916afd460f
axi_jesd_gt: synchronization support
2014-05-19 14:17:31 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
a007add714
iqcorrection: missing input signals fix
2014-05-09 11:17:50 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
1d50489870
ad9361: ml605 updates
2014-05-05 11:03:57 -04:00
5f2fb45b24
library: ported hdmi tx to altera
2014-05-02 12:07:47 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
02e8b27626
initial checkin-9250 copy
2014-04-28 21:31:16 -04:00
01de117b5f
motor_control: Changed controller to PID controller. Some estetic changes
2014-04-28 17:57:51 +03:00
fa998a406b
dma: parameter fix
2014-04-24 15:50:16 -04:00
314ec3d343
altera-9250/dma: make id width generic
2014-04-24 14:54:19 -04:00
dfc2bba335
ad9671: updates to allow default adc setup routines
2014-04-23 16:39:28 -04:00
213e852e11
motor_control: Initial commit
2014-04-18 18:57:18 +03:00
503096de18
gt: change userready on drp clock
2014-04-17 16:09:55 -04:00
570ec26798
FMCOMMS2: Added sync option
2014-04-11 18:14:48 +03:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
...
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
af07f8874f
wfifo/rfifo: asynchronous interface
2014-04-10 14:01:40 -04:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
dc7b3e085c
axi_dmac: Fix issues with non 64-bit AXI masters
...
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
36ef882da0
axi_dmac: data_mover: Improve timing
...
We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.
Also simplify a few expressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:06:44 +02:00
090d3aee04
axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
cb630e36a9
axi_dmac: src_fifo_inf: Simplify data path
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Improves timing a bit
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
f9ca4fb8be
axi_fifo: Slightly improve timing
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It is OK to overwrite invalid data with other invalid data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
4c9647f289
axi_dmac: axi_register_slice: Provide default values for registers
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
fa5ba6c09d
axi_dmac: Make cyclic mode runtime configurable
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
7ca43f4920
axi_dmac: address_generator: Make 'len' registered
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Slightly improves the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
66e6c1cc21
axi_dmac: axi_register_slice: Remove reset "latch" from datapath
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Move the datapath updates out of the else branch of the reset condition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
799d2384d8
up_xfer_cntrl: Remove extra semicolon
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
9d19145713
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-10 10:50:53 +03:00
5aac9d7288
FMCOMMS2 added sync option
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Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
e73952a694
ad9467 : initial checkin
2014-04-09 17:34:40 +03:00
8bebc5e3d4
ad9671: initial checkin
2014-04-07 13:01:10 -04:00
f8f2684b7e
up_gt: eyescan delay bug fix
2014-04-02 16:45:41 -04:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
ATofan
U-ANALOG\ACostina
Lars-Peter Clausen
Istvan Csomortani