The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
The paths from the HDMI interface registers to the IO pads are
unconstrained. This means the P&R can in theory put the register anywhere
which could lead to stability issues on the interface, depending on what
else is in the fabric. To get predictable delays for the register to IO pad
path place the register into the IOB section.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3
and AXI4, by configuring it for AXI3 there is no need for a protocol
converter inside the interconnect, that connects the DMAC to the HP port.
In addition to that also set the data width for the DMAC on the HP port side
to 64 so there is no need for a memory width converter in the interconnect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Adrian Costina
dbogdan
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen