bca8ec0160
daq2: 2014.2 and ver.d
2014-10-06 14:56:01 -04:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
525373fc04
daq3: daq2 copy
2014-10-06 10:34:00 -04:00
210da4116f
scripts: initial commit
2014-10-03 16:13:34 -04:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
89964be59e
fmcomms1: Updated project to vivado 2014.2
2014-09-30 10:32:18 +03:00
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
3c25c1171d
fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms
2014-09-26 10:28:07 -04:00
87c4c73e22
ad9434: Fix adc_clk constraint
...
ADC clock is 500 Mhz.
2014-09-25 16:54:06 +03:00
82ed885b53
ad9434: Fix SPI line physical constraints
...
SPI lines are not differential.
2014-09-25 16:53:16 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
...
All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
1d4bc47cea
ad9265: Initial commit
2014-09-23 22:51:42 -04:00
296983707b
usdrx1: Updated project to 2014.2
2014-09-23 22:45:50 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
bdf01738a1
ultrasound: disconnected ADN4670 chips from SPI lines.
...
Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
2014-09-23 22:30:42 -04:00
7e40f99fe9
fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems
2014-09-23 22:28:27 -04:00
577441bd0c
daq1: clean up dma interfaces
2014-09-23 14:23:41 -04:00
7c98a783c5
2014.2 updates
2014-09-23 12:32:33 -04:00
1682d9da10
fmcadc3: initial updates
2014-09-22 11:27:17 -04:00
5e3076d770
fmcadc3: daq2 copy
2014-09-22 11:27:16 -04:00
dd7bac41c1
daq1 : Update project to 2014.2
...
- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
2014-09-22 17:33:50 +03:00
f2cd7626f5
adi_project : ZC706 board name changed on 2014.2
2014-09-22 17:33:49 +03:00
fb5d212370
daq2/kcu105: fixed timing violations
2014-09-19 15:55:42 -04:00
751bdd6cfc
daq1: Update the constraint file
...
- tx_ref_clk and rx_sysref need to be differential
- cosmetic changes
2014-09-19 18:22:57 +03:00
f43b5d707e
fmcomms2: Reduced clock frequency for ILA to meet timing for ZED
...
Modified ZED constraints to 250 MHz for the clock from AD9361
2014-09-16 16:08:28 -04:00
d33fb07587
usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
...
GPIOs for which the directions is known, have been specifically assigned.
The SPI clock has been changed to a lower frequency.
2014-09-16 15:56:19 -04:00
d4db53c3b0
usdrx1_spi: Modified module to be compatible with altera
2014-09-16 15:53:11 -04:00
a3dbd5ac00
projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-09-16 14:59:36 +02:00
a91f4bb6b9
daq1: General updates
...
- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
2014-09-13 00:23:11 +03:00
d8651cdd2e
fmcomms2: c5soc: Set dac_util_unpack number of channels to 4
...
We only do have 4 channels in this design. Reducing the number of supported
channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment
requirement from 128bit to 64bit. We need this since applications only
expect a DMA alignment requirement of 64bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:15:12 +02:00
ecc498313c
fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects
...
We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:07 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
4c1c50788e
fmcomms5: c5soc: Fix typo
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 17:15:10 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
647a26e19c
projects/common/vc707/vc707_system_bd.tcl: Select Linux MMU settings
2014-09-10 17:40:36 +02:00
c7989925c5
fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock
...
Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
328205c31d
fmcomms2: c5soc: Set DMA transfer length to 24 bits
...
14 bits is a bit to low and we use 24 bits everywhere else as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
b58e425b44
daq2/kcu105: timing improvement -register slices hang
2014-09-08 10:24:56 -04:00
6e389b8c47
motor_control: Updated the FOC IP and the encoder connections to the IP
2014-09-06 15:58:03 +03:00
669462e0f6
ad9625x2: updates on pcores
2014-09-05 12:25:43 -04:00
72f31370ef
a5gt: ethernet-fpga lvds mode
2014-09-04 11:19:25 -04:00
3deb55bb98
a5gt: ethernet i/o changed to lvds
2014-09-04 11:19:24 -04:00
dfb94f7b68
motor_control: Modified foc_controller to be compatible with other cores
2014-09-03 12:09:37 +03:00
9f3461b130
fmcjesdadc1: Added support for KC705
2014-09-02 18:02:25 +03:00
17122661d2
fmcomms2_pr: Fix file path on ZC706/system_bd.tcl
2014-09-01 18:49:55 +03:00
2ce7695bf7
fmcjesdadc1: Initial commit of VC707 version
2014-09-01 18:47:01 +03:00
9a80fec4e4
fmcjesdadc1: Delete trailing whitespaces
2014-09-01 18:45:20 +03:00
d08d0cd70b
motor_control: added the MW FOC IP and updated the design
2014-09-01 18:35:21 +03:00
ee752ec08a
daq1: Initial commit
2014-09-01 18:34:31 +03:00
a773cc4992
usdrx1: updated project
...
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
95c143412d
fmcomms2: Modified design to work with 4 channel util_adc_pack
2014-08-29 13:53:59 +03:00
da913864c9
ad9671_fmc: updates to match recent core changes
2014-08-28 13:16:52 -04:00
5a42c10233
projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.
2014-08-27 21:46:23 +03:00
c435edf194
ad9652/zc706: fix dma write
2014-08-27 10:44:39 -04:00
7b280b3bbf
fmcomms6: zc706 build-only version
2014-08-27 10:44:37 -04:00
0e909647b4
fmcomms6: initial checkin
2014-08-27 10:44:36 -04:00
a49eb5853b
ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
...
For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
5f21f54463
fmcjesdadc1: zc706 version
2014-08-25 14:28:57 -04:00
cb29b83b05
a5gt: updates to match a5gt
2014-08-25 10:46:59 -04:00
76ffb939e5
zc706: ad9625 copy
2014-08-22 11:24:24 -04:00
fe1eaefcff
fmcomms1: zc706
2014-08-22 09:08:55 -04:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
f3f8414d81
kcu105: changes for ad_iobuf
2014-08-15 15:01:52 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
a54e4edb08
Add xfest14 PMODs project
...
This project has a SPI controller connected to each of the ZED boards PMOD
ports JA, JB, JC, JD pin 1-4. Pin 7-10 are connected to the PS7 general purpose
GPIOs, except for JC where it is connected to the PS7 UART controller.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-08-12 10:14:16 +02:00
96969079ce
a5soc: fixes for 14.0 and spi conflicts
2014-08-11 16:46:37 -04:00
902d5b0da2
prcfg: Update fmcomms2_pr for ZC706
2014-08-05 17:55:31 +03:00
9dfbf4a9a6
prcfg: Update the prcfg logic to the new ad9361 interface
2014-08-05 17:54:37 +03:00
e9f8c0fb5f
fmcomms5: ZC706 modified constraints for linux build machines
2014-08-01 18:09:55 +03:00
6c6cab0e16
fmcomms2: ZC706 modified constraints for linux build machines
...
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
2014-08-01 17:34:36 +03:00
663588eeaf
daq2/kcu105: working ddr version
2014-07-29 09:15:30 -04:00
9cdd4107cd
fmcomms5: ZC702: add reset_b and fixed system_top
2014-07-25 15:24:11 +03:00
7bee85423d
c5soc: removed stp/cdf files
2014-07-24 20:53:08 -04:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
...
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
a68f634de9
fmcomms5: Added resetb for the second AD9361
2014-07-24 17:31:30 +03:00
49a77c0413
prcfg: Generate configuration files to *.bin
2014-07-24 09:43:00 +03:00
db2386a351
daq2/kcu105: latest mig updates
2014-07-23 16:25:55 -04:00
db1c931736
ad9625_plddr: PL DDR3 fixes
...
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
4da8100fe5
ad9625_plddr: Delete trailing whitespaces.
2014-07-23 19:31:07 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
e3320c43cb
fmcomms2/c5soc: programmer file
2014-07-21 09:06:55 -04:00
9b9e0c6a56
fmcomms2/c5soc: signal tap
2014-07-21 09:06:54 -04:00
65879d621f
daq2: updates for the new hardware
2014-07-21 09:06:53 -04:00
2b6ce1e504
zc706_plddr3 : Fix axi_fifo2s_axi_mrst net
2014-07-21 15:10:36 +03:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
085512a738
fmcomms2_pr: Fix the source path for prcfg_setup
2014-07-10 17:54:41 +03:00
95701fbd0e
fmcomms2_pr : PR initial check in
2014-07-10 10:41:48 +03:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
...
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
10c21a343a
fmcomms2/c5soc: Fixed the spim0_ss_in_n value.
2014-07-08 10:07:31 +03:00
c53b257ab1
fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments.
2014-07-07 22:28:25 +03:00
c75e6b3043
kcu105 pwr-good removed
2014-07-07 09:56:13 -04:00
f2bf5ced04
ad9625: register map updates
2014-07-03 14:30:03 -04:00
f94cbbb0aa
daq2: register map updates
2014-07-03 12:36:37 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
9a08189b93
c5soc: initial a5soc copy
2014-07-01 13:09:38 -04:00
c1b7fc17f5
c5soc: initial a5soc copy
2014-07-01 13:05:26 -04:00
60dd14bcdb
a5soc: removed jtag master control
2014-07-01 12:27:37 -04:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
92e525d573
ad9250: register map updates
2014-06-25 15:24:48 -04:00
e38813fa9f
fifo- monitor status signals
2014-06-25 12:15:13 -04:00
57bb3705f2
zc706-plddr3: read changes to lower dma clock
2014-06-25 09:20:58 -04:00
3d8d576532
prcfg_script: Update the PR flow script
...
+ Make part global
+ No need the Explore directive on implementation
+ Fix some reference to pr module
+ Fix the pr_verify function
2014-06-13 20:33:59 +03:00
7efd6149f8
daq2: initial checkin
2014-06-12 15:54:25 -04:00
b1b9067512
ad9625x2_fmc: added multi-sync support
2014-06-12 15:45:35 -04:00
6ea7dd7fc3
kcu105: pwr-good added
2014-06-12 15:22:31 -04:00
6e444559b5
usdrx1: global clock fix
2014-06-10 18:09:49 +03:00
2d27f88588
ad9625_fmc, ad9625x2_fmc: initial checkin
2014-06-09 16:40:48 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
2837d788a6
mitx045: Added I2S core to the base design
2014-06-06 17:53:47 +03:00
bd8d355b05
scripts: Update adi_prcfg_project.tcl
...
Define a new parameter for the prcfg_init_workspace process:
prcfg_name_list.
2014-06-06 15:00:23 +03:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
f452e40192
scripts: Initial check in of non-project flow
...
These processes are used for projects with partial
reconfiguration. The used design flow in these cases is the
non-project (batch) design flow.
2014-06-05 14:33:27 +03:00
45325b7c0d
mitx045: minor changes in common and ADV7511 projects
2014-06-03 19:24:12 +03:00
f695a45394
global clock fix
2014-06-03 09:23:23 -04:00
f217139770
fmcomms2: added project for mini_itx, xc7z045 version
2014-06-02 14:06:10 +03:00
c52327d0c6
common,adv7511: Added mitx045 platform.
2014-06-02 11:08:03 +03:00
877b81a373
ad9625/vc707: working version
2014-05-30 15:07:23 -04:00
c789dce77e
ad9625/zc706: added pl ddr3 fifo changes
2014-05-29 12:59:29 -04:00
56ddce1e8c
dmac: create fifo interface to avoid being treated as axi control stream
2014-05-27 10:25:14 -04:00
1d53d79e25
fmcomms2/common: Fix ad9361's interface
...
Loopback the l_clk to clk. l_clk is the device sampling clock, clk is used to
synchronize the cores in case of a multiple device configuration.
2014-05-21 10:09:54 +03:00
25e4520726
fmcomms2/common: Delet trailing white spaces
2014-05-21 09:47:37 +03:00
bab90a19c2
fmcomms5/zc702: removed unused ila cores
2014-05-20 14:42:48 -04:00
7e6b4ea9d0
fmcomms5: ignore only common clock to external clocks
2014-05-19 20:38:41 -04:00
9a36075324
moved fmcomms5
2014-05-19 13:49:49 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
c5b3dd3643
vc707 base : tcl update
...
- Added missing address space
- Connect the sys_audio_clkgen/reset
2014-05-08 12:30:25 +03:00
3ac1da178e
kcu105: sane except for ddr4/ethernet
2014-05-06 15:39:05 -04:00
51c0ee1e20
ml605: tcl updates
2014-05-06 09:29:21 -04:00
e7cbaca216
ml605: initial checkin
2014-05-05 11:24:12 -04:00
53af7f3c1f
ml605: initial checkin
2014-05-05 11:20:26 -04:00
4d4f66fbdd
a5soc: increase pipeline for qsys
2014-05-04 10:38:53 -04:00
b55d0d7ad1
a5soc: constraints for false paths
2014-04-30 16:14:30 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
be69c0c330
kcu105: initial checkin
2014-04-30 14:41:39 -04:00
9900a56fa5
kcu105: initial checkin
2014-04-30 14:41:37 -04:00
0b1ce14842
a5soc: basic hardware build
2014-04-30 12:40:27 -04:00
99d66e7580
a5soc: initial-copy version
2014-04-30 12:40:26 -04:00
681e4239df
ad9671/a5gt: subclass-0 version
2014-04-28 21:31:21 -04:00
06873aeddb
ad9671/a5gt: subclass-0 version
2014-04-28 21:31:20 -04:00
d66f256f1c
9671/a5gt: 9671-sc1 version
2014-04-28 21:31:19 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Michael Hennerich
Lars-Peter Clausen
acozma
dbogdan