d4a21d9775
ad9625_fmc: constraints fix
2014-10-20 10:00:39 -04:00
b3c784f76a
ad9467_fmc: Made some cosmetic changes on the block design script.
2014-10-20 13:28:34 +03:00
4b8720b551
fmcomms2_zc706: Remove top level constraints
...
Remove all the unnecessary top level constraint definitions.
2014-10-20 13:25:01 +03:00
7115864b4c
ad9434_fmc: Remove top level constraints
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Remove all the unnecessary top level constraint definitions.
2014-10-20 13:23:37 +03:00
5deffd57b1
zed: Remove top level constraints
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Remove top level constraints from the ZED base design.
2014-10-20 13:20:27 +03:00
0c56e5b912
ad9434_fmc: Fix GPIO width
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GPIO port width is 15 instead of 32
2014-10-20 10:59:30 +03:00
7f8270d74b
ad9625_fmc: generic dma fifo for zynq and non-zynq boards
2014-10-17 14:38:16 -04:00
0b30f98640
ad9625_fmc/zc706: remove top level constraints
2014-10-17 14:38:15 -04:00
f3c9627cae
adi_project: demote reset warnings to info
2014-10-17 14:38:13 -04:00
14ccdaaa78
kcu105: removed spdif reset
2014-10-17 14:00:00 -04:00
380eeec013
daq2/kcu105: ethernet fix
2014-10-17 13:48:35 -04:00
fca0714478
adv7511/kcu105: ethernet fix
2014-10-17 13:48:33 -04:00
e73b3b52dc
kcu105: ethernet fix
2014-10-17 13:47:50 -04:00
2600b1f359
daq3: tx interleave and dma fifo axi streaming
2014-10-15 14:51:04 -04:00
6d76e0b768
zc706: remove top level constraints
2014-10-15 14:51:02 -04:00
5715c5b28f
dmafifo: axi stream interface
2014-10-15 14:50:57 -04:00
0aed11fa6c
adi_project: demote useless warnings
2014-10-15 14:50:54 -04:00
4d4a7981f2
fmcomms1: Connect DMA controller directly to the HP ports
...
The AXI DMAC controller nativly supports AXI3, there is no need to insert a interconnect to do protocol conversion.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:46:07 +03:00
7d3be14ab5
common: Connect audio clkgen reset
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While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
fd89458708
common: Set cpu interconnect strategy to minimize area
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There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
d2a04856a9
common: Fix xlconstant output pin name
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On 2014.2 xlconstant output pin name is 'dout'.
2014-10-15 15:37:06 +03:00
02802644bf
fmcjesdadc1: Fix a few warning and issue with ILA
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+ GPIO width is 15
+ Fix ILA core
2014-10-15 15:37:05 +03:00
865cbab3a2
ad9671_fmc: Updated a5gt project with start of frame information
2014-10-15 10:53:33 +03:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
f528873fa9
fmcomms2: Add an additional SPI interface for up/down converter board
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Supported carriers are: ZC706, ZC702 and Zed.
2014-10-10 18:47:07 +03:00
ca4c961891
fmcomms2: Use ad_iobuf instance on system_top
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Use ad_iobuf instance on system top, instead of separate IOBUF instances.
2014-10-10 18:45:39 +03:00
e21d26e456
fmcomms2: Cosmetic changes
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Get rid of unwanted whitespaces.
2014-10-10 18:25:17 +03:00
fe8a076b2e
fmcomms2: Cosmetic changes on *_bd.tcl script
2014-10-10 17:06:32 +03:00
7a9e694446
fmcomms2: Connect DMA directly to the HP ports
...
The DMA controller is able to send AXI3 compatible requests, no need to add
a interconnect for protocol conversion in between the DMA controller and the
HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:14 +03:00
87047fd83e
fmcomms2: Set dac_unpack channels to 4
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There are only 4 DAC channels in the fmcomms2 design, so set the number of
channels of the dac_unpack core to 4. This slightly reduces resource usage
as well as reducing the DMA alignment requirement from 128bit to 64bit. The
later value is what existing applications expect the alignement requirement
to be.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:06 +03:00
43e9b0c7a6
common: Disable TTC0 MMIO routing for PS7
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We do not use the ttc0 to MMIO routing, but it is enabled by default, so
explicitly disable it.
2014-10-10 16:19:51 +03:00
e361bbbd04
Revert "fmcomms2_udc: Initial check in"
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This reverts commit ddc7c845e9
2014-10-10 14:48:55 +03:00
7659f3438c
AD9467: Fixup swapped net names
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-10-10 12:33:07 +03:00
adf4893a27
usdrx1: remove constraints and other changes
2014-10-09 15:25:08 -04:00
ddc7c845e9
fmcomms2_udc: Initial check in
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FMCOMMS2 with an additional SPI port for the up/down converter board
2014-10-09 19:01:22 +03:00
6f77af4aff
fmcjesdadc1: Upgrade project to 2014.2
2014-10-09 18:55:27 +03:00
2da395926e
fmcomms2: Upgrade project to 2014.2
2014-10-09 18:54:33 +03:00
4f6aa159b8
mitx045: Base design now support 2014.2
2014-10-09 15:11:28 +03:00
edeeafa47d
ad9671_fmc: Added sof information to the AD9671 driver
2014-10-09 14:52:25 +03:00
072e11c661
ad9467_fmc: Upgrade the axi_quad_spi core
2014-10-08 15:22:58 +03:00
fc38249150
ad9467 ZED: Fix over range signal path, and the dma interface.
2014-10-08 11:24:44 +03:00
15db557bd6
ad9467 ZED: Cosmetic changes on bd script.
2014-10-08 11:24:32 +03:00
82717b354a
ad9467_fmc : Upgrade project to 2014.2
2014-10-08 11:21:43 +03:00
b2d0260130
ad9467_fmc: Prevent to use concatenation module on SPI interface
...
This module cause unnecessary issues during version upgrades.
2014-10-08 11:20:45 +03:00
27153fff41
ad9625x2_fmc: updated to 2014.2
2014-10-07 16:05:09 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
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axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
95842b8949
ad9434_fmc: Fix adc_valid signal path
2014-10-07 18:02:33 +03:00
115f33b8d6
ad9434_fmc: Fix pin constraints for ZC706
2014-10-07 17:58:29 +03:00
c1213ffe71
ad9434_fmc: Fix SPI interface
2014-10-07 17:51:14 +03:00
cd42345324
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
bca8ec0160
daq2: 2014.2 and ver.d
2014-10-06 14:56:01 -04:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
525373fc04
daq3: daq2 copy
2014-10-06 10:34:00 -04:00
210da4116f
scripts: initial commit
2014-10-03 16:13:34 -04:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
89964be59e
fmcomms1: Updated project to vivado 2014.2
2014-09-30 10:32:18 +03:00
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
3c25c1171d
fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms
2014-09-26 10:28:07 -04:00
87c4c73e22
ad9434: Fix adc_clk constraint
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ADC clock is 500 Mhz.
2014-09-25 16:54:06 +03:00
82ed885b53
ad9434: Fix SPI line physical constraints
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SPI lines are not differential.
2014-09-25 16:53:16 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
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All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
1d4bc47cea
ad9265: Initial commit
2014-09-23 22:51:42 -04:00
296983707b
usdrx1: Updated project to 2014.2
2014-09-23 22:45:50 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
bdf01738a1
ultrasound: disconnected ADN4670 chips from SPI lines.
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Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
2014-09-23 22:30:42 -04:00
7e40f99fe9
fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems
2014-09-23 22:28:27 -04:00
577441bd0c
daq1: clean up dma interfaces
2014-09-23 14:23:41 -04:00
7c98a783c5
2014.2 updates
2014-09-23 12:32:33 -04:00
1682d9da10
fmcadc3: initial updates
2014-09-22 11:27:17 -04:00
5e3076d770
fmcadc3: daq2 copy
2014-09-22 11:27:16 -04:00
dd7bac41c1
daq1 : Update project to 2014.2
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- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
2014-09-22 17:33:50 +03:00
f2cd7626f5
adi_project : ZC706 board name changed on 2014.2
2014-09-22 17:33:49 +03:00
fb5d212370
daq2/kcu105: fixed timing violations
2014-09-19 15:55:42 -04:00
751bdd6cfc
daq1: Update the constraint file
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- tx_ref_clk and rx_sysref need to be differential
- cosmetic changes
2014-09-19 18:22:57 +03:00
f43b5d707e
fmcomms2: Reduced clock frequency for ILA to meet timing for ZED
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Modified ZED constraints to 250 MHz for the clock from AD9361
2014-09-16 16:08:28 -04:00
d33fb07587
usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
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GPIOs for which the directions is known, have been specifically assigned.
The SPI clock has been changed to a lower frequency.
2014-09-16 15:56:19 -04:00
d4db53c3b0
usdrx1_spi: Modified module to be compatible with altera
2014-09-16 15:53:11 -04:00
a3dbd5ac00
projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-09-16 14:59:36 +02:00
a91f4bb6b9
daq1: General updates
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- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
2014-09-13 00:23:11 +03:00
d8651cdd2e
fmcomms2: c5soc: Set dac_util_unpack number of channels to 4
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We only do have 4 channels in this design. Reducing the number of supported
channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment
requirement from 128bit to 64bit. We need this since applications only
expect a DMA alignment requirement of 64bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:15:12 +02:00
ecc498313c
fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects
...
We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:07 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
4c1c50788e
fmcomms5: c5soc: Fix typo
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 17:15:10 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
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This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
647a26e19c
projects/common/vc707/vc707_system_bd.tcl: Select Linux MMU settings
2014-09-10 17:40:36 +02:00
c7989925c5
fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock
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Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
328205c31d
fmcomms2: c5soc: Set DMA transfer length to 24 bits
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14 bits is a bit to low and we use 24 bits everywhere else as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
b58e425b44
daq2/kcu105: timing improvement -register slices hang
2014-09-08 10:24:56 -04:00
6e389b8c47
motor_control: Updated the FOC IP and the encoder connections to the IP
2014-09-06 15:58:03 +03:00
669462e0f6
ad9625x2: updates on pcores
2014-09-05 12:25:43 -04:00
72f31370ef
a5gt: ethernet-fpga lvds mode
2014-09-04 11:19:25 -04:00
3deb55bb98
a5gt: ethernet i/o changed to lvds
2014-09-04 11:19:24 -04:00
dfb94f7b68
motor_control: Modified foc_controller to be compatible with other cores
2014-09-03 12:09:37 +03:00
9f3461b130
fmcjesdadc1: Added support for KC705
2014-09-02 18:02:25 +03:00
17122661d2
fmcomms2_pr: Fix file path on ZC706/system_bd.tcl
2014-09-01 18:49:55 +03:00
2ce7695bf7
fmcjesdadc1: Initial commit of VC707 version
2014-09-01 18:47:01 +03:00
9a80fec4e4
fmcjesdadc1: Delete trailing whitespaces
2014-09-01 18:45:20 +03:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina
Paul Cercueil
Michael Hennerich
acozma