pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Istvan Csomortani	aa7b0bb4dd	VC707 basesys: General fixes, actual status: working - Add an auxiliary cpu interconnect - Add an auxiliary interrupt concatenation module - Add new MIG file, current frequency of the DDR interface is 100 Mhz - Memory interconnect optimisation strategy is 'Maximize Performance'	2014-03-24 13:07:48 +02:00
Istvan Csomortani	75963ab376	Initial check in of VC707 base project - All source files for the VC707 base project - Update the common base system to the new naming convention	2014-03-10 17:26:17 +02:00

Author

SHA1

Message

Date

Istvan Csomortani

aa7b0bb4dd

VC707 basesys: General fixes, actual status: working

- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'

2014-03-24 13:07:48 +02:00

Istvan Csomortani

75963ab376

Initial check in of VC707 base project

- All source files for the VC707 base project
	- Update the common base system to the new naming convention

2014-03-10 17:26:17 +02:00

2 Commits (54b2cd74bfde4125a28aebd0154c2454c298b147)