4 Commits (53cb087b9ce632eb5f2d8fb7d85f687a6b79d548)

Author	SHA1	Message	Date
Adrian Costina	09ad67bfd7	adrv9009zu11eg: Make the project more parametrizable	2019-12-04 14:59:18 +02:00
Adrian Costina	0cb5c0bdaf	adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency	2019-11-27 16:27:44 +02:00
Adrian Costina	dfe3258a4f	adrv9009zu11eg: Add axi_sysid	2019-11-19 10:29:57 +02:00
Adrian Costina	a589a2c7eb	adrv9009_zu11eg_som: Change design partitioning ... Create a structure similar with ADRV936x projects	2019-11-14 15:25:23 +02:00