pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Laszlo Nagy	4026eaa19b	ad9081_fmca_ebz: Fix device clocks termination The device clocks are AC coupled LVDS lines without external termination. For proper operation internal differential termination must be enabled, the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V	2020-10-06 16:13:21 +03:00
Laszlo Nagy	b1f62f09ac	ad9081_fmca_ebz:vcu118: initial version Use over-writable parameters from the environment. e.g. make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8	2020-03-10 18:19:03 +02:00

Author

SHA1

Message

Date

Laszlo Nagy

4026eaa19b

ad9081_fmca_ebz: Fix device clocks termination

The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V

2020-10-06 16:13:21 +03:00

Laszlo Nagy

b1f62f09ac

ad9081_fmca_ebz:vcu118: initial version

Use over-writable parameters from the environment.

      e.g.
        make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
        make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
        make JESD_MODE=8B10B  RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8

2020-03-10 18:19:03 +02:00

2 Commits (537a284115eeb30b2d0031c6e7d453ab5496d39b)