AndreiGrozav
e1f0b301d3
Tools version upgrade
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Vivado 2018.2 -> Vivado 2018.3
Quartus 18.0 -> Quartus 18.1
2019-04-12 10:48:50 +03:00
Istvan Csomortani
302ec5d68a
adi_project_alt: Update Quartus version to 18.0.0
2018-08-23 18:41:48 +03:00
Rejeesh Kutty
8e042193be
DE10: Initial commit
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These modifications were taken from the old dev branch.
2018-04-11 15:09:54 +03:00
Istvan Csomortani
0026617033
scripts:adi_project: Use default strategies for synth and impl
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To reduce compilation time use default stratagies for synthesis and
implementation. If a project will require custom strategies, enable it
just for that particular project.
This modification will affect both Intel and Xilinx projects.
2018-04-11 15:09:54 +03:00
Istvan Csomortani
47e95fc4a9
scripts: Update tools for the next release
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The next supported tool versions are:
+ Vivado 2017.4.1
+ Quartus 17.1
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen
9c38fb81fb
adi_project_alt.tcl: Disable a few warnings generated by standard components
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Some of the standard Quartus components (especially the Merlin cores) generate
quite a few synthesis warnings. Lets assume these are false positives and
disable the warnings.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:18:40 +02:00
Rejeesh Kutty
ffb6cd4b0b
scripts- add a5soc device
2017-06-13 09:54:01 -04:00
Rejeesh Kutty
688758e6c6
scripts/adi_project_alt- add a5soc, a5gt
2017-06-09 16:19:29 -04:00
Rejeesh Kutty
ca20309166
adi_project_alt: add c5soc
2017-06-08 15:02:24 -04:00
Rejeesh Kutty
e9c49f667f
altera- 16.1.2 & a10soc
2017-06-06 12:20:44 -04:00
Adrian Costina
54a53c015a
scripts: changed adi_project_create command to adi_project_altera
2017-06-06 17:29:12 +03:00
Rejeesh Kutty
eadbf9ae30
altera- remove default assignments from procedure
2017-06-05 15:25:38 -04:00
Rejeesh Kutty
1b1c7ffa61
adi_project- altera version
2017-06-05 15:13:21 -04:00