e616c8da0b
m2k: Remove channel pack core for now
...
We always have both ADC channels enabled and the cpack core takes up a fair
amount of space, so remove it for now. Might come back later when we really
need it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
efa2d0c006
m2k: Connected adc/dac resets to decimation/interpolation cores
2017-04-18 12:17:39 +02:00
500112f79b
m2k: Renamed l_clk to adc_clk and rst to adc_rst
2017-04-18 12:17:39 +02:00
6a49aefb6c
m2k: Updated project to use new tx path with serdes
2017-04-18 12:17:39 +02:00
b58a5c37eb
m2k: Reduce AXI interconnect utilization
...
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
e04793b6eb
m2k: standalone: Assign 0 to unused GPIO inputs
...
To avoid warnings from the tools assign 0 to the unused GPIO inputs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:16:25 +02:00
24a7d8ea9d
m2k: Remove redundant s_axi_{aclk,aresetn} assignment
...
ad_cpu_interconnect will make sure to connect the clock and the reset of
the AXI interface. Remove the redundant manual assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-28 11:14:48 +02:00
09bcecb6ed
m2k: Simplify DMA connection to HP1
2017-03-15 15:11:30 +02:00
2a9b3cea09
m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use
2017-03-14 13:57:50 +02:00
f7c2bd943b
m2k: Enable AD9963 adc data path processing.
...
- part of the path is the sign extension module. Without it, the triggering doesn't work correctly
2017-03-13 23:18:29 +02:00
59dda01419
m2k: Disabled DDS cores for the generic project
2017-02-28 10:10:28 +02:00
545e458997
m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage
2017-02-27 14:17:29 +02:00
eda585f0e4
m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2
2017-02-27 14:16:32 +02:00
908da60ab6
m2k: zed, changed constraints so they are the same with the ZED default configuration
...
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
2017-02-27 14:13:34 +02:00
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
e215a091b2
m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints
2017-02-13 12:02:59 +02:00
4e62fb0ef3
m2k: Add reset circuitry on the logic_analyzer clock domain
2017-02-13 12:02:11 +02:00
6aadb49e80
m2k: Remove use board flow from the standalone version
2017-02-02 12:58:58 +02:00
0d0c3e99fd
m2k: Added I2C pull-ul, removed SLEW constraints
2017-02-02 12:35:46 +02:00
5155b3f46d
m2k: Fix gpio buswidth
2017-02-01 17:43:01 +02:00
cfff70d358
M2K: Update standalone project
...
- configured PS7 similar to pluto. Added specific constraints instead of default PS7
- moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1]
2017-02-01 14:27:11 +02:00
6bdd853b88
m2k: Updated PS7 configuration
2017-01-31 23:08:53 +02:00
b14d740f87
M2K: initial commit
2017-01-31 16:43:40 +02:00
Lars-Peter Clausen
Adrian Costina
Rejeesh Kutty