Commit Graph

1103 Commits (5192adf5a7a7de1436252bc33ad7301339fb6fab)

Author SHA1 Message Date
Rejeesh Kutty 4f918cdce9 2014.4.1 ultrascale updates 2015-02-26 16:10:57 -05:00
Rejeesh Kutty 847c2e049a kcu105: removed lutram constraints 2015-02-26 16:09:55 -05:00
Istvan Csomortani 1613f7fb41 cftl_cip: Add util_pmod_fmeter IP to library
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
Lars-Peter Clausen abde4048e0 fmcomms1: Add extra AXI slice on ADC DMA path
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-20 16:43:45 +01:00
Rejeesh Kutty b9d16a7eb1 scripts: renaming board parameters 2015-02-20 09:12:30 -05:00
Lars-Peter Clausen 65bda6505e axi_dmac: Correctly handle shutdown for the request splitter
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen 731e1c0996 axi_dmac: Use internal enable signal for the request generator
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen 582ea06918 axi_dmac: request_generator: Stop generating requests when disabled
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.

So just stop generating burst requests once the DMAC is being disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen aa594e15f3 axi_dmac: fifo_inf: Handle overflow and underflow correctly
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:21 +01:00
Rejeesh Kutty 6edcaa478a adi_ip: updates for 2014.4 2015-02-19 11:11:39 -05:00
Rejeesh Kutty 288f5378ff rfsom: schematic changes 2015-02-18 14:32:41 -05:00
Rejeesh Kutty 93e2bcd911 rfsom: schematic changes 2015-02-18 14:32:30 -05:00
Rejeesh Kutty 383cf3b3a3 rfsom: schematic changes 2015-02-18 14:32:20 -05:00
Rejeesh Kutty d2e9b1fe03 rfsom: schematic changes 2015-02-18 14:32:04 -05:00
Istvan Csomortani 3113abf038 cftl_cip: Add gpio counter for CN0332
Add a counter core to the design, to support the CN0332 pmod with a speed sensor.
Change a naming for the custom cores.
2015-02-18 18:24:46 +02:00
Rejeesh Kutty 9cdec38532 gt- report device type 2015-02-17 11:43:57 -05:00
Rejeesh Kutty 2442b6e929 gt- report device type 2015-02-17 11:43:50 -05:00
Rejeesh Kutty fccadcec31 jesd_gt: lpm/dfe programmable 2015-02-13 11:33:25 -05:00
Rejeesh Kutty de043ce130 gt_channel: lpm/dfe programmable 2015-02-13 11:33:04 -05:00
Rejeesh Kutty 870ebdb562 up_gt: support lpm mode 2015-02-12 16:21:11 -05:00
Rejeesh Kutty 1e7c9a3924 gt_es: support lpm mode - 2/2 2015-02-12 16:20:43 -05:00
Rejeesh Kutty 0a8e6f62ef gt_es: support lpm mode - 1/2 2015-02-12 15:15:18 -05:00
Istvan Csomortani c908cea801 Merge branch 'master' into dev 2015-02-09 10:01:39 +02:00
Rejeesh Kutty 9e2e2ef44e xfer-logic: stretch toggles to allow capture 2015-02-06 22:15:16 -05:00
Rejeesh Kutty e9231c8f36 xfer-logic: stretch toggles to allow capture 2015-02-06 22:15:14 -05:00
Rejeesh Kutty e111e1336e conflicts- 2015-02-06 22:14:21 -05:00
Rejeesh Kutty 8839c8b18c xfer-logic: stretch toggles to allow capture 2015-02-06 22:07:00 -05:00
Rejeesh Kutty 8050a14bd8 xfer-logic: stretch toggles to allow capture 2015-02-06 22:06:56 -05:00
Rejeesh Kutty 518d842af9 upack: initial commit 2015-02-06 15:15:33 -05:00
Istvan Csomortani 2d607d765b cftl_cip: Add a clock input to the device core, for the SPI clock.
This clock can be adjustable from the system_project.tcl
2015-02-04 14:55:17 +02:00
Istvan Csomortani d02c21b426 util_pmod_adc: General update
Redesign the state machine, rename constant and variable names, add notes and description.
2015-02-04 14:49:16 +02:00
Rejeesh Kutty 996e1b7970 rfsom: constraint updates 2015-02-03 14:20:34 -05:00
Istvan Csomortani 890bb1da75 daq2: Add support for VC707 2015-01-29 18:33:27 +02:00
Adrian Costina fd2ab02174 cftl_std: Added in the constraint file comments regarding supported CFTLs 2015-01-29 16:27:43 +02:00
Istvan Csomortani 8ccab473eb README.md: General update
/dev branch supports Vivado 2014.4
2015-01-29 12:46:19 +02:00
Istvan Csomortani d69d105b5d vc707_common: Fix address mapping
The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
2015-01-29 12:22:06 +02:00
Istvan Csomortani e8ff30119d vc707_xdc: Delete unnecessary clock definition 2015-01-29 11:39:10 +02:00
Istvan Csomortani 6c8ea24f20 common: Update VC707 base design to 2014.4 2015-01-28 16:24:52 +02:00
Istvan Csomortani e1d8dd10a9 daq2: Initial check in of the VC707 based project
NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 16:24:06 +02:00
Istvan Csomortani 96899313d8 axi_dmac: Fix constraint
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
Istvan Csomortani b10ba49425 axi_dmac: Fix constraint related issue
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
2015-01-23 18:44:17 +02:00
Istvan Csomortani d5bd485624 axi_dmac: Fix eot issue under 2014.4
Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
2015-01-23 18:39:33 +02:00
Istvan Csomortani 659e0cca4e cftl_cip: Initial check in.
Project cftl_cip supports the following Circuits from the Lab pmods:
 + EVAL-CN0350-PMDZ
 + EVAL-CN0335-PMDZ
 + EVAL-CN0336-PMDZ
 + EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
Adrian Costina 463a3bbc88 cftl_std: Updated project. Switched to PS7 gpio. Renamed signals. 2015-01-23 14:11:33 +02:00
Adrian Costina 9672271155 fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
2015-01-23 13:30:56 +02:00
Adrian Costina 5a77ab0161 a5gt:common: Added phy reset signal from ethernet in pin assignments 2015-01-23 12:31:41 +02:00
Adrian Costina 050f17e034 a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2 2015-01-23 12:30:16 +02:00
Rejeesh Kutty d6499e202c Merge remote-tracking branch 'origin/hdl_2014_r2' into dev 2015-01-15 15:48:36 -05:00
Rejeesh Kutty 5a1819ed6e fifo2s: qualify last with valid 2015-01-15 15:42:10 -05:00
Rejeesh Kutty 8fedb5b41c fifo2s: qualify last with valid 2015-01-15 09:34:43 -05:00