Lars-Peter Clausen
5250635162
cn0363: Fix ad_iobuf signal names
...
The signal names for the ad_iobuf were recently changed, adjust the cn0363
project accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-27 13:25:19 +02:00
Lars-Peter Clausen
73d7bc111e
cn0363: Add missing Makefiles
...
Those were accidentally overlooked during the initial commit of the project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-26 18:44:24 +02:00
Adrian Costina
77eff35d67
motcon2_fmc: Fixed constraint for renamed port
2015-05-23 19:02:48 +03:00
Adrian Costina
29ca9e4b8c
vc707: common, fixed address range for flash
2015-05-23 00:14:08 +03:00
Adrian Costina
8bd5fa5802
kc705: Common, fixed address range for the flash. Changed the start address so that it won't interfere with other cores
2015-05-23 00:10:06 +03:00
Istvan Csomortani
f91fbf1bc1
ad9434_zc706: Fix SPI interface
2015-05-22 12:31:48 +03:00
Rejeesh Kutty
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
Rejeesh Kutty
ad3198f623
a10gx: top level fixes
2015-05-21 14:06:15 -04:00
Lars-Peter Clausen
c9832d2f84
Remove ad7175_zed project
...
This project has been superseded by the cn0363 project and can be removed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen
c53f8c15ee
Add CN0363 project
...
Add support for the CN0363 (colorimeter) board connected to the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen
6b9906b22b
Refresh Makefiles
...
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Adrian Costina
ebbc0c6ed5
fmcomms5: zc706, removed debug related ila, as the pins were removed from the AD9361 IP
2015-05-21 14:19:22 +03:00
Istvan Csomortani
a047d3990a
fmcadc2_vc707: Fix interrupts
...
+ Remove some trailing whitespaces
+ Fix interrupt connections
2015-05-21 11:03:16 +03:00
Rejeesh Kutty
19b094cab5
daq2/a10gx- added jesd align
2015-05-20 15:39:27 -04:00
Rejeesh Kutty
f1c30ac225
daq2/a10gx- qsys updates
2015-05-20 14:24:49 -04:00
Rejeesh Kutty
4927ca85c2
projects- jesd-align port name change
2015-05-20 14:24:26 -04:00
Rejeesh Kutty
52b6077a46
a10gx- 15.0 updates
2015-05-19 15:12:23 -04:00
Rejeesh Kutty
0805da3b6b
fmcomms2/rfsom- enable dac delay
2015-05-18 16:45:54 -04:00
Rejeesh Kutty
3e51d29f75
enable/txnrx- tdd changes
2015-05-18 14:28:20 -04:00
Adrian Costina
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Rejeesh Kutty
672a5a4dfa
a10gx- updates
2015-05-14 14:35:43 -04:00
Rejeesh Kutty
b311b9dac6
a10gx- updates
2015-05-14 14:35:42 -04:00
Rejeesh Kutty
3226ca4374
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
Rejeesh Kutty
c28ff2ff9a
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
Rejeesh Kutty
16541335e6
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
Rejeesh Kutty
2cd1d8a591
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
Rejeesh Kutty
0a6efaccca
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
Rejeesh Kutty
848dac70d5
a10gx: updates--
2015-05-11 11:56:27 -04:00
Rejeesh Kutty
dc0eea5f0f
a10gx: updates--
2015-05-11 11:56:26 -04:00
Rejeesh Kutty
bdc3f3d807
a10gx: updates--
2015-05-11 11:56:24 -04:00
Rejeesh Kutty
75e055dab9
daq2/a10gx- initial commit
2015-05-11 11:56:23 -04:00
Rejeesh Kutty
515dfd88d4
a10gx- added
2015-05-11 11:56:22 -04:00
Adrian Costina
14b721682d
motcon1_fmc: Removed
2015-05-11 18:02:52 +03:00
Adrian Costina
3d4e9eb36a
ac701: common, commit ethernet reset pin
2015-05-11 16:41:28 +03:00
Istvan Csomortani
15618c9edf
daq2 : Integrate the DACFIFO into the supported projects.
...
+ All pack/unpack logic is made by the cpack and upack modules.
+ The DAC FIFO is integrated between the TX DMA and cpack.
+ All the top files are updated, all the projects compiled successfully.
2015-05-11 12:20:50 +03:00
Istvan Csomortani
bad821ba1c
sys_dmafifo: Update the p_sys_dacfifo process
...
Update the ports and parameters at util_dacfifo instantiation.
2015-05-11 12:20:47 +03:00
Istvan Csomortani
d9a124b767
fmcomms2_zc706: TDD integration, initial commit.
2015-05-11 12:20:45 +03:00
Adrian Costina
00335a2af2
Makefile: Fix ZC706 Makefiles with propper address for the mig file
2015-05-11 10:25:07 +03:00
Rejeesh Kutty
81a20b4abb
rfsom- apisys lb updates
2015-05-08 15:22:17 -04:00
Adrian Costina
d515ab1b61
adv7511: AC701, update project to work at full HD resolution
2015-05-08 18:53:47 +03:00
Adrian Costina
293ec6a319
fmcomms2: c5soc project updated to 14.1
2015-05-08 17:44:16 +03:00
Adrian Costina
91279253ef
Makefiles: Added mig project file as a dependency for Microblaze based projects. Also updated usdrx1 a5gt Makefile
2015-05-08 15:31:40 +03:00
Adrian Costina
573acc8af6
usdrx1: A5GT project updated to 14.1
2015-05-08 15:04:44 +03:00
Adrian Costina
1c9b41db6f
fmcjesdadc1: A5GT project, added modular sgdma for Ethernet, nios configured for linux
2015-05-08 14:51:24 +03:00
Adrian Costina
68570c1815
vc707: Common system mig, updated datawidth to 256 from 128
2015-05-08 10:51:27 +03:00
dbogdan
d7a0f1ffe3
projects/imageon_loopback: Add the option of setting hdmi_iic_rstn externally.
2015-05-07 15:17:16 +03:00
Adrian Costina
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
Adrian Costina
4f75414a1a
fmcomms1: Removed constraints that are not needed
2015-05-05 23:39:08 +03:00
Adrian Costina
1fcaf8fb63
fmcomms1: Updated AC701 project to meet timing. Reduced FIFO size for AD9643 DMA to 8
2015-05-05 23:37:01 +03:00
Adrian Costina
90a5bb81b6
cftl_cip: Updated project to work with the new util_pmod_adc core
2015-05-05 23:34:52 +03:00
Adrian Costina
95805f21fa
adv7511: Fixed system_top for mitx045 board
2015-05-05 10:08:11 +03:00
Adrian Costina
3517b6941c
adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
2015-05-05 10:06:26 +03:00
Rejeesh Kutty
319f821fab
zc706pr - makefile
2015-05-04 13:41:03 -04:00
Rejeesh Kutty
ab85e2ba36
zc706pr - 706 partial reconfiguration
2015-05-04 12:36:57 -04:00
Rejeesh Kutty
e489090fbb
scripts- initialize prcfg list
2015-05-04 12:34:19 -04:00
Rejeesh Kutty
2a8703763e
zc706pr - 706 partial reconfiguration
2015-05-04 12:33:28 -04:00
Rejeesh Kutty
c3dd9258e7
zc706: project mode
2015-05-04 10:25:12 -04:00
Rejeesh Kutty
62acd37fee
zc706: project mode
2015-05-04 10:25:07 -04:00
Istvan Csomortani
e7a0da9089
fmcomms2 : Verify the existence of the PR license
...
The fmcomms2 runs by default on PR mode, if the project script does not find a PR license, will implement just the default mode.
2015-05-04 15:12:38 +03:00
Rejeesh Kutty
4bb26caa13
itx045: default install
2015-05-01 16:19:10 -04:00
Rejeesh Kutty
ad551a0073
itx045: updates
2015-05-01 16:18:43 -04:00
Rejeesh Kutty
aced144916
itx045: updates
2015-05-01 16:18:23 -04:00
Rejeesh Kutty
ff443655ca
itx045: add ps7 settings
2015-05-01 16:17:59 -04:00
Rejeesh Kutty
26fb85583b
adi_project- prefix directory for gitignore & make clean
2015-05-01 13:18:12 -04:00
Rejeesh Kutty
00cafd4df0
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:18 -04:00
Rejeesh Kutty
3641d8f714
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:11 -04:00
Rejeesh Kutty
75a81d67d8
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:07 -04:00
Rejeesh Kutty
0dc4c9cda9
adi_project: added partial reconfiguration
2015-05-01 12:21:59 -04:00
Rejeesh Kutty
140c622c8b
prcfg: common files
2015-05-01 11:48:09 -04:00
Rejeesh Kutty
a8d4c916c1
fmcomms2_bd: remove axi3 switch
2015-05-01 11:47:29 -04:00
Adrian Costina
3b58785368
daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints
2015-04-30 12:14:03 +03:00
Adrian Costina
e332fa01c8
ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection
2015-04-30 12:11:46 +03:00
dbogdan
1df48a2e6e
Add hdmiio_int pin.
2015-04-29 18:50:28 +03:00
Adrian Costina
19ef85cec3
vc707: Changed mig project to use BANK_ROW_COLUMN, as it seems this mode gives best performance
2015-04-28 17:15:58 +03:00
Adrian Costina
288b9cccff
Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
2015-04-28 15:22:37 +03:00
Adrian Costina
252aa135eb
ad9739a: Changed dma and interconnect clock to 200mhz. Removed div_clk constraint, as it is autodetected
2015-04-28 15:14:31 +03:00
Adrian Costina
3fdda617a4
fmcomms1: updated common, changed DMAC fifo size and wfifo reset signal source
...
- changed DMAC FIFO size to 16, as it should be large enough
- connected wfifo reset to adc_rst from axi_ad9643 core
2015-04-28 14:58:04 +03:00
Adrian Costina
37bfb2ef4b
ad9265: Updated common, wfifo is reset by the adc_rst signal from axi_ad9265 core
2015-04-28 14:53:12 +03:00
dbogdan
1eebfd3155
projects/imageon_loopback: Initial commit.
2015-04-28 10:32:28 +03:00
Adrian Costina
e51edfbadb
adv7511: KC705 mdio pin name fix
2015-04-27 11:21:36 +03:00
Adrian Costina
7e6f2bfa15
ad9265: Updated constraints file.
2015-04-27 11:20:42 +03:00
Rejeesh Kutty
272148eee5
rfsom: sdio 50mhz
2015-04-23 15:30:50 -04:00
Rejeesh Kutty
7611c2ae17
kcu105: ddr mig rbc to rcb
2015-04-23 15:30:48 -04:00
Istvan Csomortani
bb185296d7
fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples.
...
The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
2015-04-23 18:00:00 +03:00
Lars-Peter Clausen
f232a36141
common: Place HDMI interface registers into the IOB
...
The paths from the HDMI interface registers to the IO pads are
unconstrained. This means the P&R can in theory put the register anywhere
which could lead to stability issues on the interface, depending on what
else is in the fabric. To get predictable delays for the register to IO pad
path place the register into the IOB section.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
Lars-Peter Clausen
bd6c76f4ab
fmcomms5: Set DMA AXI type to AXI3 on ZYNQ
...
The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3
and AXI4, by configuring it for AXI3 there is no need for a protocol
converter inside the interconnect, that connects the DMAC to the HP port.
In addition to that also set the data width for the DMAC on the HP port side
to 64 so there is no need for a memory width converter in the interconnect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
Lars-Peter Clausen
4ed7c9aee9
fmcomms2_pr: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
Lars-Peter Clausen
558f2e89af
imageon: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
Lars-Peter Clausen
1bb5b6e55f
adv7511: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
Adrian Costina
a61a195e3f
Makefiles: Updated makefiles to add the new constraints as dependecies
2015-04-23 11:16:39 +03:00
Rejeesh Kutty
e25cfb9d9f
rfsom: ddr configuration
2015-04-22 13:45:11 -04:00
Istvan Csomortani
a100ecd308
util_dacfifo: Update BRAM DAC Fifo
...
The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
Lars-Peter Clausen
3fd830b038
fmcomms2: Use AXI3 interface for the DMA on ZYNQ
...
On ZYNQ the HP interconnects have a AXI3 interface. The DMA controller
supports both AXI4 and AXI3. By switching to AXI3 there is no need to create
a protocol converter between the DMA and the HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
Lars-Peter Clausen
71d4f3a474
fmcomms2: Don't mark synchronous paths as asynchronous for the DMAs
...
The AXI master interface and the register map AXI slave interface use the
same clock. No need to mark the interfaces as asynchronous. This removes the
need for CDC logic on those paths.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
Adrian Costina
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
...
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Istvan Csomortani
8b5d1a8693
fmcadc2: Connect the second CS line for the external SPI interface
2015-04-15 19:08:17 +03:00
Adrian Costina
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
Lars-Peter Clausen
afea42f444
rfsom: Use interface connection for the I2S stream
...
Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:26 +02:00
Lars-Peter Clausen
90e132d203
mitx045: Use interface connection for the I2S stream
...
Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00