aa180fb272
axi_adrv9001: Let gate signals have initial value, useful for simulation
2021-05-26 15:44:45 +03:00
b85784ebe8
axi_adrv9001: rx: calculate ramp value based on received value
2021-05-26 15:44:45 +03:00
9a93b56882
axi_adrv9001:rx: Add reset to link layer
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Fix random valid signals after resets on the Rx interface.
2021-05-26 15:44:45 +03:00
4c35af74d4
axi_adrv9001:rx:phy: do not generate valid while in reset
2021-05-26 15:44:45 +03:00
32dbde6945
axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1
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This commit removes the deadlock created while trying to use the Rx2/Tx2
channels without the Rx1/Tx1 channels enabled first.
2021-05-26 15:44:45 +03:00
1502b940d3
common/up_dac_common: Expose r1_mode in up clock domain to prevent deadlock
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If R1 mode is first syncronized to the dac clock domain will prevent its
usage if the dac clock is missing. In such case the synchronization will not
propagate.
2021-05-26 15:44:45 +03:00
d9bc014c98
adrv9001/zcu102: Enable independent Tx from Rx in CMOS mode
2021-05-26 15:44:45 +03:00
08b0d19731
axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks
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Depending on FPGA technology the physical layer uses different
deserialization factors and corresponding clock division factors to
divide the source synchronous interface clock. This must be
exposed to software so it can act on it while setting the DDS rate.
Xilinx CMOS clock ratio - 4
Xilinx LVDS clock ratio - 4
Intel CMOS clock ratio - 1
2021-05-26 15:44:45 +03:00
568bef4a38
adrv9001/a10soc: Initial version
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This project supports CMOS mode only.
2021-05-26 15:44:45 +03:00
5d008c3eca
Correct constraints file pin mapping
2021-05-25 16:27:58 +03:00
0ad691a603
ad9081_fmca_ebz/zcu102: Differentiate parameters based on lane rate
2021-05-14 15:39:40 +03:00
8183599b51
ad9081_fmca_ebz/zcu102: Fix typo
2021-05-14 15:39:40 +03:00
cf7f45ffcc
ad9081_fmca_ebz: Fix for F=8
2021-05-14 15:39:40 +03:00
9b50e2baa5
util_adxcvr/util_adxcvr_xch: Fix typo
2021-05-14 15:39:40 +03:00
7b2ba41bdd
ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing
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This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
2021-05-14 15:39:40 +03:00
e1b73545e4
util_adxcvr: GTY TX phase and delay alignment circuit power down.
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Tied High when a) TX buffer bypass is not in use;
see UG578
2021-05-14 15:39:40 +03:00
ef69fe36db
util_adxcvr: Add PPF1_CFG parameter
2021-05-14 15:39:40 +03:00
eba3409d78
ad9082_fmca_ebz: Use 9081 system_bd, updated comments
2021-05-14 15:39:40 +03:00
0d9e38bdbe
ad9081_fmca_ebz: Update path to common block design
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Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
2021-05-14 15:39:40 +03:00
680d28476c
ad9081_fmca_ebz: Add LANE_RATE param to all projects
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The block design expects a lane rate to be set in the system project.
2021-05-14 15:39:40 +03:00
bd6ec360e2
ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link
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Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs
Organize XCVR params based on lane rate
2021-05-14 15:39:40 +03:00
693c002668
ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR
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Remove Xilinx PHY and simplify project
2021-05-14 15:39:40 +03:00
d92f925b06
ad9081_fmca_ebz: Disable XBAR from DAC TPL
2021-05-14 15:39:40 +03:00
001e7a52b1
util_adxcvr: Add LANE_RATE parameter so it can be used for automatic constraint generation
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Add separate LANE_RATE for TX and RX
2021-05-14 15:39:40 +03:00
cb5e66ff9c
xilinx/util_adxcvr: 204C link support for GTY4
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Set channel parameters based on link mode (1 - 204b or 2 - 204c).
2021-05-14 15:39:40 +03:00
2d13b5b8cd
xilinx/axi_adxcvr: Add 204C support, increase version to 17.3.a
2021-05-14 15:39:40 +03:00
77a5edaa83
scripts/adi_board.tcl: In 204C do not connect SYNC
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Take link mode parameter from util_adxcvr, check it against the axi_adxcvr.
2021-05-14 15:39:40 +03:00
60612720cd
jesd204/jesd204_common/sync_header_align: Initial version
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This module creates sync header alignment described in section 7.6.1 of
the JESD 204C specification.
The alignment relies on the bitslip capability of the connected
transceiver.
2021-05-14 15:39:40 +03:00
0c0c6843e3
jesd204/axi_jesd204: Complete clock definitions in out of context mode
2021-05-14 15:39:40 +03:00
e08ca2fc20
jesd204: Add out of context constraint file for link layer cores
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For the out of context flow it is important to have all clocks defined
at the interface, especially if the clock are used in the other constraints.
2021-05-14 15:39:40 +03:00
b4c5031272
axi_pulse_gen: Fix typo introduced in c235e5e58
2021-05-10 13:26:30 +03:00
37238916df
Testbenches: Unify and optimize HDL testbenches
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Create a common 'run_tb.sh' script to be called by every testbench.
Unify file and testbenches names.
Fix util_pack/cpack_tb.
Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui)
Add ascript for that generates output in xml format (used by CI tools).
2021-05-07 19:53:14 +03:00
c235e5e583
axi_pwm_gen: Initial commit
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axi_pwm_gen is based on util_pulse_gen, it introduces the option of
phase option between pulses(PWMs) and external synchronization.
Documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-05-07 19:09:32 +03:00
1db04a47b8
ad9083_evb: Update parameters to 10Gpbs lane rate
2021-04-19 13:21:34 +03:00
8335e1bd9a
sysid: Make sure gitbranch_string is always declared
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Parsing of not existed "gitbranch_string" fails the build process.
2021-03-24 13:34:32 +02:00
6a374ef457
ad469x/zed: Add multicycle path constraint
2021-03-22 13:05:05 +02:00
9413afa41c
jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg
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get_cell on i_lmfc/cdc_sync_stage1_reg doesn't return anything because design was updated.
This generates a CRITICAL WARNING and since the constraint it not necessary anymore, it can be deleted.
2021-03-22 10:55:00 +02:00
cdd6c92357
xilinx/axi_adxcvr: Increase version to 17.02.a to show PRBS capability
2021-03-22 10:17:10 +02:00
5f2681314f
xilinx/axi_adxcvr/axi_adxcvr_up: Fix force error control bit
2021-03-22 10:17:10 +02:00
40baa63f0f
adrv2crr_fmcomms8: Fix system_top.v
2021-03-19 17:56:28 +02:00
93044adddf
axi_spi_engine: almost full and almost empty is generated by the util_axis_fifo
2021-03-18 18:53:35 +02:00
d91b50071f
axi_spi_engine: Fix IRQ generation
2021-03-18 18:53:35 +02:00
22ce3ef9ce
axi_spi_engine: Fix level/room width for the CDC FIFOs
2021-03-18 18:53:35 +02:00
c718ba91f1
axi_adrv9001: Add status bit for Tx clocking
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If Tx source synchronous clock is not routed through clock capable pins
the interface and driving logic must run on the Rx interface clock.
This introduces a dependency, Rx interface must be bring up before the
Tx. In this mode a Tx only operation is not possible.
This is done through a synthesis parameter.
Expose this parameter to the software so it can query if the limitations
exists in the implementation.
2021-03-17 16:34:12 +02:00
c9ca1ac00a
util_axis_fifo: Improve GUI layout in Vivado
2021-03-12 15:06:45 +02:00
a1773c661c
adrv9009zu11eg_crr: Update spi
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Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
3dce87d09b
ad9083: Add reference design for ad9083 eval board
2021-03-10 10:52:03 +02:00
dcec4fe1b7
adrv9001/zc706: Fix spaces
2021-03-10 10:35:52 +02:00
dc186645d8
adrv9001/zc706: Fix comments HPC to LPC
2021-03-10 10:35:52 +02:00
61c07ff9f1
util_axis_fifo: Add REMOVE_NULL_BEAT_EN feature
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If the REMOVE_NULL_BEAT_EN is set, in FIFO mode, all the beats with a
NULL TKEEP will be removed from the AXI stream.
This feature is used initially in data_offload, to create a continues and
cyclic TX data stream for DACs, when the IPs in the path have different data
widths.
2021-03-08 11:32:40 +02:00
Laszlo Nagy
Owen McAree
AndreiGrozav
stefan.raus
vladimirnesterov
Sergiu Arpadi
Istvan Csomortani