1bc8a41aea
vc709_carrier: Add vc709 carrier ( #788 )
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Added vc709 carrier to the projects/common folder location.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-02 12:05:42 +02:00
70cc53bbc8
ad_ip_jesd204_tpl_dac: Move external dac sync bit
2021-10-27 18:36:47 +03:00
7b0922e4dc
library/common/up_adc_common.v: Remove tabs
2021-10-27 18:36:47 +03:00
a9c9636780
library/common/up_dac_common.v: Cleanup spaces
2021-10-27 18:36:47 +03:00
9b7c2852b6
adxcvr: Increase version to 17.5.a
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Add suport for XCVR phase adjust buffer status:
- Expose TXBUFSTATUS and RXBUFSTATUS
- Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
2021-10-27 14:40:50 +03:00
c5d216bba9
adrv9001/zcu102: Enable independent TX mode in CMOS
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For CMOS case, lane rates are so low that reference clock of the source
synchronous interface can be routed on non-clock routes. The delays on
the clock line are adjusted by the digital interface tuning controlled
through software.
Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal
placement which causes large skew between clocks at the serdes pins.
2021-10-27 14:40:08 +03:00
d493b724f2
axi_adrv9001/adrv9001_rx.v: Simplify clocking
2021-10-27 14:40:08 +03:00
03682f6193
projects/adrv9001/zcu102/lvds_constr.xdc: Fix timing constraints
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1. Reduce max allowed skew between source synchronous clocks that can
occur due PCB differences. 250ps represents a difference more than an
inch.
2. In order to reduce skew between source synchronous clock and the
divided clock instruct the tool to use a common clock root for them.
2021-10-27 14:40:08 +03:00
6a5d2f76d5
data_offload: Fix oversized TX input transactions
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Signed-off-by: David Winter <david.winter@analog.com>
2021-10-27 14:26:22 +03:00
cd6024b341
Revert "data_offload: Fix oversized inputs in TX mode"
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This reverts commit 0e8f55b2d7
2021-10-27 14:26:22 +03:00
d4126739b4
projects: remove hardcoded div_clk from xcvr
2021-10-27 12:11:22 +03:00
52df3c4937
ad463x_data_capture: Remove tb
2021-10-26 15:58:54 +03:00
cb861f5299
ad463x: Fix readme
2021-10-26 15:42:57 +03:00
076e81a17c
library: Add link to wiki for IPs
2021-10-25 10:44:53 +03:00
15a6480601
ad4630_fmc: Initial commit
2021-10-18 16:13:31 +03:00
6a526f4bb6
ad463x_data_capture: Initial commit
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IP required to support echo and master clock mode
2021-10-18 16:13:31 +03:00
5ac64b021f
spi_engine_execution: Delete control loop-back in sdi_data_valid generation
2021-10-18 16:13:31 +03:00
6570c23a76
axi_spi_engine: Add generic config params
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The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
2021-10-18 16:13:31 +03:00
f86ae28e50
spi_engine/data_reorder: Initial commit
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In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.
The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
2021-10-18 16:13:31 +03:00
6565c5d018
library/tb: Improve run_tb.sh
2021-10-18 16:13:31 +03:00
ff090b60ef
daq2/zcu102: Fix the ad9144 data offload to use internal BRAM
2021-10-15 15:03:22 +03:00
3640c2b584
daq2/kcu105: Fix the ad9144 data offload to use internal BRAM
2021-10-15 15:03:22 +03:00
6ad54c1056
daq2/kc705: Fix the ad9144 data offload to use internal bram
2021-10-15 15:03:22 +03:00
907cd613aa
daq2/zc706: Increase BRAM utilization to 52%
2021-10-15 15:03:22 +03:00
e34346360d
scripts: Add logic for vivado version check
2021-10-12 14:34:11 +03:00
812baf9022
Revert "data_offload: Fix timing violation"
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This reverts commit 1fe0d5f8e0
2021-10-08 11:42:05 +03:00
5db7574dce
scripts/adi_board.tcl: For older families stick with axi_interconnect
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SmartConnect has higher resource utilization and worse timing closure
that makes several zed based projects to fail timing.
2021-10-07 14:18:49 +03:00
dbd5ffe4ed
jesd204_rx: fixed makefile
2021-10-07 12:48:08 +03:00
0c6c28ed84
jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes
2021-10-06 15:49:56 +03:00
9295218a64
projects/ad9081_fmca_ebz: Updated makefiles
2021-10-05 16:56:57 +03:00
51b643b978
Makefile: Fix misc makefiles from projects and library
2021-10-05 14:24:48 +03:00
22e1366bfc
jesd204/jesd204_rx: Define tie off values for unused ports
2021-10-05 14:09:51 +03:00
aa93c17cdc
jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation
2021-10-05 14:09:51 +03:00
3a1babe366
ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock
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Reset transceiver with a pulse
2021-10-05 14:09:51 +03:00
2562aead32
ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock
2021-10-05 14:09:51 +03:00
8d547f31e1
ad9081_fmca_ebz/vck190: Initial version
2021-10-05 14:09:51 +03:00
6c58a8d1ab
ad9081_fmca_ebz/common: Add Versal transceiver support
2021-10-05 14:09:51 +03:00
1a9e7dbeb4
jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP
2021-10-05 14:09:51 +03:00
56a25afa68
common/vck190: Initial version
2021-10-05 14:09:51 +03:00
6a681b9e8d
common/vmk180_es1: Initial version
2021-10-05 14:09:51 +03:00
833e5f0aff
common/vmk180: Initial version
2021-10-05 14:09:51 +03:00
2fec1356d6
scripts/adi_project_xilinx.tcl: VCK190 support
2021-10-05 14:09:51 +03:00
222c5782b6
scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode
2021-10-05 14:09:51 +03:00
011c8c1f36
scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support
2021-10-05 14:09:51 +03:00
c22f622599
scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect
2021-10-05 14:09:51 +03:00
4d12c4d99a
scripts/adi_xilinx_device_info_enc.tcl: Add Versal support
2021-10-05 14:09:51 +03:00
2b242bf06f
scripts/adi_ip_xilinx.tcl: Enable auto family support
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Some IPs like JESD link layer were marked as not supported on Versal devices by
the current flow while other not (e.g. TPL).
The auto family support seems to workaround this issue.
2021-10-05 14:09:51 +03:00
08c2ce75fe
scripts/adi_board.tcl: Switch cpu_interconnect to SmartConnect
2021-10-05 14:09:51 +03:00
aaaba50f83
scripts/project-xilinx.mk: Update target to xsa and cleanup list
2021-10-05 14:09:51 +03:00
57546b853d
.gitignore: Ignore Versal files
2021-10-05 14:09:51 +03:00
hotoleanudan
Laszlo Nagy
Filip Gherman
David Winter
LIacob106
sergiu arpadi
Istvan Csomortani
Mihaita Nagy