Commit Graph

31 Commits (501903bc817b24c42d9bce31a16441a27da0f2a0)

Author SHA1 Message Date
Filip Gherman 4790d334ad dac_fmc_ebz: NUM_LINKS added to system_top.v 2022-02-09 12:23:12 +02:00
Filip Gherman 3ff2887485 dac_fmc_ebz_vcu118: Initial commit 2022-02-08 14:34:47 +02:00
Filip Gherman 694ebbfbfc dac_fmc_ebz_bd.tcl: Updated bd for multiple tx_ref_clk 2022-02-08 14:34:17 +02:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Istvan Csomortani 6d19041b21 dac_fmc_ebz: QPRO is using apply_instance_preset 2020-08-11 10:14:18 +03:00
Istvan Csomortani 4684dc03ce dac_fmc_ebz/a10soc: Use balanced optimization mode
Always a good idea to start from default, and change optimization mode
of the tool if it's strict necessary.
2020-03-17 17:25:02 +00:00
Istvan Csomortani 253a8cb6ee dac_fmc_ebz/a10soc: Tool expect that all config parameters exists on top entity 2020-03-17 17:25:02 +00:00
Laszlo Nagy 35412c81a9 dac_fmc_ebz: drive spi_en pin automatically based on FMC board selected
spi_en is active ...
   ... high for AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ,
   ... low for AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
2020-03-03 15:49:30 +02:00
Laszlo Nagy 46a413d9a5 dac_fmc_ebz/common/config.tcl: fix typo 2020-02-13 11:32:38 +02:00
Prasahnt Sivarajah 9ab4c0c783 dac_fmc_ebz: Passthrough GPIO signal for bypass 2019-12-06 11:04:45 +02:00
Prasahnt Sivarajah 8b45d17eb9 dac_fmc_ebz: Only create dummy ports for unused
lanes
2019-12-06 11:04:45 +02:00
AndreiGrozav 3c46cc9347 dac_fmc_ebz: Add project info to sys_id
Add project device and mode info to sys_id custom string
2019-10-15 17:08:53 +03:00
AndreiGrozav 58b846faae dac_fmc_ebz: Add build time config option 2019-10-15 17:08:53 +03:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani ec67a381e4 adi_project: Rename the process adi_project_altera to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Laszlo Nagy 3bf120123b dac_fmc_ebz: update Makefiles 2019-06-06 11:45:05 +03:00
Laszlo Nagy 1541b918d8 dac_fmc_ebz: added README 2019-06-06 11:45:05 +03:00
Lars-Peter Clausen 6d31a437aa dac_fmc_ebz: Add initial Arria10 SoC support
Add support for the Arria 10 SoC development kit to the dac_fmc_ebz
project.

This allows to use the following FMC boards on the Arria 10 SoC development
Kit carrier:
  * AD9135-FMC-EBZ
  * AD9136-FMC-EBZ
  * AD9144-FMC-EBZ
  * AD9152-FMC-EBZ
  * AD9154-FMC-EBZ
  * AD9171-FMC-EBZ
  * AD9172-FMC-EBZ
  * AD9173-FMC-EBZ

Note that the board in its default configuration is not fully compatible with the
mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is
required. The rework concerns the LA01 and LA05 pins, which by default are
not connected to the FPGA. The changes required are:

  LA01_P_CC
    R612: R0 -> DNI
    R610: DNI -> R0
  LA01_N_CC
    R613: R0 -> DNI
    R611: DNI -> R0
  LA05_P
    R621: R0 -> DNI
    R620: DNI -> R0
  LA05_N
    R633: R0 -> DNI
    R632: DNI -> R0

The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are:
  * The DAC txen signals are connected to different pins
  * The polarity of the spi_en signal is active low instead of active high
  * The maximum lane rate is up to 15.4 Gpbs

To accommodate this all 4 possible txen signals as well as the spi_en
signal are connected to GPIOs. Software can decide how to use them
depending on which FMC board is connected.

Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
  * A10SoC: 14.2 Gbps
2019-06-06 11:45:05 +03:00
Lars-Peter Clausen c2c78b1b73 dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support
Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the
ZCU102 and ZC706 carrier boards.

The project is called dac_fmc_ebz as the intention is to support all DAC
FMC evaluation boards with this project since they are sufficiently similar
to be supported by the same design.
This project will successively extended to add support for more boards.

The desired DAC device and JESD operation mode must be selected from the following
file:
  ./common/config.tcl

This design can support the following FMC boards which are all pin
compatible:
  * AD9135-FMC-EBZ
  * AD9136-FMC-EBZ
  * AD9144-FMC-EBZ
  * AD9152-FMC-EBZ
  * AD9154-FMC-EBZ
  * AD916x-FMC-EBZ
  * AD9171-FMC-EBZ
  * AD9172-FMC-EBZ
  * AD9173-FMC-EBZ

Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other
boards use 8 lanes.

This project assumes that the transceiver reference clock and SYSREF are
provided via the clock distribution chip that is found on the
ADxxxx-FMC-EBZ board.

In terms of pin connections between the FPGA and the FMC board the
AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ.

The main differences are:
  * The DAC txen signals are connected to different pins
  * The polarity of the spi_en signal is active low instead of active high
  * The maximum lane rate is up to 15.4 Gpbs

To accommodate this 5 txctrl signals as well as the spi_en signal are connected
to GPIOs. Software can decide how to use them depending on which FMC board
is connected.

Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
  * ZC706:  10.3125 Gbps
  * ZCU102: 15.4 Gbps (max AD9172 lanerate)

* SPI and GPIOs to PMOD header support

Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102
and zc706 carriers.

This is can be used to control additional external hardware like a clock
chip or an analog front-end.

This is especially useful on FMC boards that do not feature a clock
generator chip.

The pin out is:
	PMOD  1: SPI clock
	PMOD  2: SPI chipselect
	PMOD  3: SPI MOSI
	PMOD  4: SPI MISO
	PMOD  7: GPIO 0
	PMOD  8: GPIO 1
	PMOD  9: GPIO 2
	PMOD 10: GPIO 3

The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2019-06-06 11:45:05 +03:00