45dae0f3d3
ad9081_fmca_ebz/common: Connect sync at TPL level
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Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
2022-02-07 19:14:01 +02:00
80b3fc2d0a
ad9081_fmca_ebz: versal: Remove unused GT reset input pin
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Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-22 16:18:29 +02:00
e00def31d0
ad9081_fmca_ebz: versal: Remove external gt_reset logic
2021-11-19 14:01:48 +02:00
0b9631f1f7
ad9081_fmca_ebz: versal: Rename nets
2021-11-19 14:01:48 +02:00
ca6248ba88
ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL
2021-11-19 14:01:48 +02:00
731ed0a7a5
ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver
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Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.
Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-19 14:01:48 +02:00
1d951cfbae
ad9081_fmca_ebz/vck190: Change default profile to 2 lanes
2021-11-19 14:01:48 +02:00
adad6c930d
ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters
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For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-12 13:04:57 +02:00
3a1babe366
ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock
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Reset transceiver with a pulse
2021-10-05 14:09:51 +03:00
2562aead32
ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock
2021-10-05 14:09:51 +03:00
6c58a8d1ab
ad9081_fmca_ebz/common: Add Versal transceiver support
2021-10-05 14:09:51 +03:00
edd2956d58
data_offload: Fix util_[cu]pack offset to TDD syncs
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-30 14:45:54 +03:00
b9554a9a5a
ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-30 14:45:54 +03:00
e9e278c898
ad9081_fmca_ebz: Remove bypass gpio
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
2178191610
ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine
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Memory requirements are the same as with the dacfifo (1 MiB).
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
cf7f45ffcc
ad9081_fmca_ebz: Fix for F=8
2021-05-14 15:39:40 +03:00
680d28476c
ad9081_fmca_ebz: Add LANE_RATE param to all projects
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The block design expects a lane rate to be set in the system project.
2021-05-14 15:39:40 +03:00
693c002668
ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR
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Remove Xilinx PHY and simplify project
2021-05-14 15:39:40 +03:00
d92f925b06
ad9081_fmca_ebz: Disable XBAR from DAC TPL
2021-05-14 15:39:40 +03:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
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adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
6b13b32f24
ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
2021-03-04 11:13:29 +02:00
ddd8a14790
ad9081_fmca_ebz: Remove system reset from Xilinx PHY
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Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
2021-02-05 15:24:15 +02:00
af3e1c7003
ad9081_fmca_ebz/a10soc: Np 12 support
2021-02-05 15:24:15 +02:00
d0f8a81b2f
ad9081_fmca_ebz: Np 12 support
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204B functional
204C functional
2021-02-05 15:24:15 +02:00
0fd5590e56
ad9081_fmca_ebz: a10soc: Initial version
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Parametrizable project with default profile of:
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
3dd370a27c
ad9081_fmca_ebz: enable xbar in DAC TPL
2020-11-27 09:45:11 +02:00
e9f319e3d7
ad9081_fmca_ebz: HP0 is already initialized in ZC706
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On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
2020-11-12 15:46:27 +02:00
e8f6523197
ad9081_fmca_ebz: adapt to renamed tpl core
2020-05-20 19:08:25 +03:00
cbb23c7b67
ad9081_fmca_ebz: fix Xilinx PHY resets
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Avoid clock domain crossing on resets.
2020-04-23 17:21:05 +03:00
e112a03d85
ad9081_fmca_ebz: Whitespace cleanup
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Clear extra lines and whitespaces at end of lines.
2020-04-23 17:21:05 +03:00
7df4caf8b0
ad9081_fmca_ebz: Added parameter description
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Add parameter description to project and common block design file
2020-04-23 17:21:05 +03:00
e433d3f808
ad9081_fmca_ebz: expose PLL selection as a parameter
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On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
0 - CPLL
1 - QPLL0
2 - QPLL1
Since the selection of line rate is available from the project also the
PLL selection must be exposed.
2020-04-23 17:21:05 +03:00
b774e1ca7d
ad9081_fmca_ebz: enable IQ rotation
2020-04-03 11:16:37 +03:00
f3630dd95b
ad9081_fmca_ebz: common block design
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Parametrizable block design with selectable JESD physical layer between
Xilinx Phy and ad_utilxcvr.
2020-03-10 18:19:03 +02:00
Laszlo Nagy
stefan.raus
David Winter