zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,589 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

6 Commits (500112f79b951e7727091abca8d51808c87e15cc)

Author SHA1 Message Date
Adrian Costina 6a49aefb6c m2k: Updated project to use new tx path with serdes 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen b58a5c37eb m2k: Reduce AXI interconnect utilization 
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Adrian Costina eda585f0e4 m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2 2017-02-27 14:16:32 +02:00
Adrian Costina 908da60ab6 m2k: zed, changed constraints so they are the same with the ZED default configuration 
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
 2017-02-27 14:13:34 +02:00
Rejeesh Kutty c598e84258 remove processing order (no clock def dependency) 2017-02-22 16:02:08 -05:00
Adrian Costina b14d740f87 M2K: initial commit 2017-01-31 16:43:40 +02:00