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11 Commits (500112f79b951e7727091abca8d51808c87e15cc)

Author SHA1 Message Date
Adrian Costina 500112f79b m2k: Renamed l_clk to adc_clk and rst to adc_rst 2017-04-18 12:17:39 +02:00
Adrian Costina 6a49aefb6c m2k: Updated project to use new tx path with serdes 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen b58a5c37eb m2k: Reduce AXI interconnect utilization 
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 24a7d8ea9d m2k: Remove redundant s_axi_{aclk,aresetn} assignment 
ad_cpu_interconnect will make sure to connect the clock and the reset of
the AXI interface. Remove the redundant manual assignments.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-03-28 11:14:48 +02:00
Adrian Costina 09bcecb6ed m2k: Simplify DMA connection to HP1 2017-03-15 15:11:30 +02:00
Adrian Costina 2a9b3cea09 m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use 2017-03-14 13:57:50 +02:00
Adrian Costina f7c2bd943b m2k: Enable AD9963 adc data path processing. 
- part of the path is the sign extension module. Without it, the triggering doesn't work correctly
 2017-03-13 23:18:29 +02:00
Adrian Costina 59dda01419 m2k: Disabled DDS cores for the generic project 2017-02-28 10:10:28 +02:00
Adrian Costina eda585f0e4 m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2 2017-02-27 14:16:32 +02:00
Adrian Costina 4e62fb0ef3 m2k: Add reset circuitry on the logic_analyzer clock domain 2017-02-13 12:02:11 +02:00
Adrian Costina b14d740f87 M2K: initial commit 2017-01-31 16:43:40 +02:00