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14 Commits (4e77acf282d0174f26736ac9702cd080e2b4237a)

Author SHA1 Message Date
Adrian Costina d43ba5d26e axi_ad9963: Integrated ADC/DAC clock enables 2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 3ab1e392c5 axi_ad9963: Disable delay_clk port when IODELAYs are unused 
The delay_clk is only used internally when the IODELAYs are enabled. This
means the port has no function when the IODELAYs are disabled so hide the
port in that case.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:40 +02:00
Adrian Costina 3c13aa49eb axi_ad9963: Changed TX path from serdes to ddr. 
- remove delay control related logic
 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 547dc04857 axi_ad9963: Sign extend ADC data when processing is bypassed 
Match the behaviour of the processing data path and sign extend the output
data to 16-bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 72cdd846b0 axi_ad9963: Allow to disable the IDELAYs on the ADC data path 
Not all designs need the IDELAYs. Disabling them can reduce power consumption of the system.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Adrian Costina 094872619d axi_ad9963: Separated adc/dac clock and reset 2017-04-18 12:17:39 +02:00
Adrian Costina 9f8fd5c922 axi_ad9963: updated tx path 
- removed pll for power saving, added serdes circuitry instead
 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 3e0b337eae axi_ad9963: Remove extra pipeline stages on register read path 
The register read logic is not that complicated that it needs two extra
pipeline stages. It can easily be condensed into a single combinatorial and
still meet timing with large margins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 64dfa0432d axi_ad9963: Disable unused features of the register map 
Disable registers in the register map which are not needed for this core.
This reduces the utilization of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints 
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
 2017-03-30 16:16:02 +03:00
Lars-Peter Clausen 983e56d72c ad9963: Remove localparams from module parameter list 
Declaring local parameters in the module parameter list is not valid
verilog. For some reasons Vivado accepts it nevertheless so the code has
worked so far. But this is not true for other tools, so move the local
parameter definitions inside the module body.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-03-30 11:40:28 +02:00
Adrian Costina fb945ac51c axi_ad9963: Initial commit 2017-01-31 16:18:58 +02:00