4c8206608c
axi_jesd_gt- separate es-axi
2015-08-13 13:03:51 -04:00
e4b0710923
axi_jesd_gt- per lane split-up
2015-08-13 13:03:51 -04:00
f59058dd8a
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-06 15:17:19 +03:00
ad80561379
TDD_regmap: Fix CDC for control signals
2015-08-06 15:16:39 +03:00
e19d476b58
TDD_regmap: Fix addresses
2015-08-06 15:15:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
d5d7a24483
util_cpack: Added reset interface
2015-07-28 11:00:54 +03:00
caca364c61
ad9652- iqcor iqsel changes
2015-07-24 08:35:13 -04:00
144b8f7383
ad9643- iqcor iqsel changes
2015-07-24 08:34:52 -04:00
649297a0e3
ad_iqcor- changes
2015-07-23 16:20:46 -04:00
cd5ce3349f
iqcor- move i/q sel inside the module
2015-07-23 15:55:45 -04:00
901bcb2c06
dma- constraints modifications
2015-07-22 12:46:06 -04:00
3d7afb8fc5
jesd-xcvr: constraints modifications
2015-07-22 12:46:06 -04:00
6352884398
jesd-xcvr: common align function
2015-07-22 12:46:06 -04:00
a4461545fa
axi-ip: constraints - altera
2015-07-22 12:46:06 -04:00
ac39329046
axi_spdif_rx: Fix the pl330_dma control path
...
- fix pl330_dma control path
- delete unused control_reg bits
- change the port name spdif_rx_i_osc to spdif_rx_i_dbg
- version_reg is read only
2015-07-22 17:59:52 +03:00
559893c0a3
altera- obsolete cores
2015-07-21 11:04:26 -04:00
86dabbe5fc
jesd-align-- xilinx/altera merge
2015-07-21 10:57:00 -04:00
3a4581a8df
axi-xcvr: removed xcvr compoents
2015-07-21 10:56:04 -04:00
264f9ffbfc
ip_alt- avalon/reset definitions
2015-07-21 10:55:13 -04:00
3101045109
qsys- library group
2015-07-17 10:07:15 -04:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
31584cf27e
ad9680- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
60c344cea6
ad9144- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
29c6e90d38
util_bsplit: remove avalon streaming interface
2015-07-15 09:44:57 -04:00
af898de818
axi_jesd_xcvr: remove avalon streaming interface
2015-07-15 09:44:56 -04:00
ea57e49da7
axi_ad9250: remove avalon streaming interface
2015-07-15 09:44:54 -04:00
6e3817d419
axi_jesd_xcvr: individual reset control
2015-07-13 10:04:34 -04:00
8d6c39d307
ad9680- remove avalon streaming
2015-07-13 10:03:38 -04:00
c69e36314c
ad9144- remove avalon streaming
2015-07-13 10:03:16 -04:00
9d95ddc620
reset and clock additions
2015-07-09 14:29:08 -04:00
d6d263341e
signal tap needs another method
2015-07-08 15:47:47 -04:00
b25b2e3020
registers for signal tap
2015-07-08 15:47:45 -04:00
b4eb7465ed
library: Add missing Makefiles for axi_spdif_rx, util_jesd_align, util_jesd_xmit
2015-07-08 10:48:58 +03:00
23428ac48b
transceiver constraints for sysref
2015-07-07 15:25:36 -04:00
ea2bd71904
synchronize up signals separately
2015-07-07 12:51:13 -04:00
c1fcbeec8e
library/axi_jesd_xcvr: interface name matching
2015-07-07 10:21:53 -04:00
b106b8a8f4
library/axi_jesd_xcvr: updates
2015-07-06 13:51:55 -04:00
c67ca682a4
hw.tcl- added
2015-07-06 13:51:55 -04:00
1cfe6fe792
axi_jesd_xcvr: initial commit
2015-07-06 13:51:55 -04:00
3a5da47239
xcvr- initial checkin
2015-07-06 13:51:55 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
7376218e01
axi_spdif_rx: Initial commit
...
NOT tested.
2015-07-03 17:46:45 +03:00
896888d495
axi_mc_current_monitor: updated ad7401 driver to send unsigned data
2015-07-02 14:23:19 +03:00
a497dcabb5
axi_ad9361: Bring up the tdd_enable bit
...
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 13:52:00 +03:00
23034965c8
axi_hdmi_tx_es: Drop strange port initializers
...
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
cb03152f1f
axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
...
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
cf6052e2a8
axi_hdmi_tx: Add control to bypass chroma sub-sampler
...
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen