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25 Commits (4b8f3f06f7763410bdc5be21a1cf82e9d4d1f3fd)

Author SHA1 Message Date
Iulia Moldovan 68461110aa Replace link in license header from master to main 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2024-01-16 16:48:45 +02:00
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 15:22:26 +03:00
Iulia Moldovan 27bb69b44c Add copyright and license to .sdc files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 10:41:40 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-11 15:17:41 +03:00
ladace 34984e67c2
Quartus: Updated to Quartus Standard 22.1 (#1108) 2023-04-05 09:36:46 +03:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-01-27 11:54:05 +02:00
laurent-19 1eb5f4985b projects/common: Add build files templates carriers. Modified Quartus Versions 
The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
	  vck190, vcu118, vcu128, vmk180,
	  zc702, zc706, zcu102, zed

* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
  according to last commit update

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2022-10-05 10:47:21 +03:00
laurent-19 6b94259a52 projects/common: Add system_top _project templates 
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct code and modify according to guidelines

* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct/Add missing wrapper ports and iobufs

* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

ac701/system_top.v: Change top based on previous projects

 * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

projects/common: Modify templates to build without errors

* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
	 system_project: Added adi_board, adiobuf sourcing
	 system_top: Removed hdmi, i2c, fanpwm, spdif ports
		     according to base design
* c5soc: Added version settings
	 Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
	    system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
	 Removed unnecessary ports

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Delete microzed vmk_es templates

* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2022-09-20 17:00:49 +03:00
PopPaul2021 c5045d17b9
arradio_c5soc: axi_hdmi_tx as framereader (#920) 2022-04-20 12:11:31 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files 
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-07-28 17:56:07 +02:00
AndreiGrozav a765a9c709 arradio: Add i2c interface 2017-06-29 17:26:58 +03:00
Rejeesh Kutty ca536d50ac altera 16.1 c5soc updates 2017-06-08 15:03:03 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c7351f3ce3 arradio/c5soc- remove qsys files 2017-03-20 15:56:07 -04:00
Rejeesh Kutty 589e6b53d8 arradio/c5soc- qsys-script flow 2017-03-20 15:42:33 -04:00
Rejeesh Kutty 7dfa8c599f arradio/c5soc- updated to new framework/16.0 2017-03-20 12:15:18 -04:00
Rejeesh Kutty 12f44ccbcc arradio/c5soc- critical warnings fix 2017-03-20 12:14:21 -04:00
Rejeesh Kutty 89b20f2a35 c5soc- remove unused hps ports 2016-05-09 13:54:08 -04:00
Adrian Costina 43e03ca6f7 arradio: Updated project 
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
 2016-02-16 14:50:23 +02:00
Adrian Costina a0e67aad56 c5soc: Updated common design 2015-11-24 13:22:01 +02:00
Rejeesh Kutty a8a71b4971 alt-tq: common file 2015-06-04 11:00:25 -04:00
dbogdan 5a42c10233 projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI. 2014-08-27 21:46:23 +03:00
Rejeesh Kutty a388ccab0a fmcomms2/c5soc: initial checkin 2014-07-02 14:56:00 -04:00
Rejeesh Kutty c1b7fc17f5 c5soc: initial a5soc copy 2014-07-01 13:05:26 -04:00