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3040 Commits (4a5b7fc7230845801a81c4d058f20726bcb44ba8)

Author SHA1 Message Date
AndreiGrozav 13a35f7a2a altera/ad_serdes_clk: The IO_PLL reset is active heigh 2016-09-16 14:20:39 +03:00
Istvan Csomortani 858ea09048 altera/ad_serdes_in: Fix some typos 2016-09-16 10:56:16 +03:00
Rejeesh Kutty 2a7bc31c01 pzsdr1- disable gpreg constraints 2016-09-15 13:49:04 -04:00
Rejeesh Kutty a2d15acb89 ad_serdes- altera/xilinx sync 2016-09-15 13:33:55 -04:00
Rejeesh Kutty 67d4e71ff0 pzsdr1- disable gpreg constraints 2016-09-15 12:41:40 -04:00
Rejeesh Kutty 63696c1a28 alt_serdes- data-width parameter 2016-09-15 11:12:18 -04:00
Rejeesh Kutty 02dfd2d2e2 altera/ad_serdes_out- sample transmit order 2016-09-15 10:28:34 -04:00
Rejeesh Kutty 5986f45cba altera/ad_serdes_out- updates 2016-09-15 09:38:11 -04:00
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
Istvan Csomortani 3b0c1e02fc axi_dacfifo: Move IP to library/xilinx 2016-09-15 11:38:16 +03:00
Istvan Csomortani 3cbbc771a8 axi_adcfifo: Move IP to library/xilinx 2016-09-15 11:36:47 +03:00
Rejeesh Kutty fe133a7c39 v2001- parameter defines 2016-09-14 15:47:45 -04:00
Rejeesh Kutty 16046a984c alt_serdes- updates 2016-09-14 12:05:48 -04:00
Rejeesh Kutty 4a6b554c0a ad_serdes- updates 2016-09-14 11:12:53 -04:00
Adrian Costina 631923e9f0 usb_fx3: Update to Vivado 2016.2 2016-09-14 15:41:27 +03:00
Adrian Costina 343056b674 axi_usb_fx3: Update IP to work with 2016.2 2016-09-14 15:40:42 +03:00
Istvan Csomortani 9118ca3986 version_upgrade: Update MOTCON2 to 2016.2 2016-09-14 10:58:06 +03:00
Rejeesh Kutty a0318ae868 ad_serdes_clk- syntax errors 2016-09-13 14:02:11 -04:00
Istvan Csomortani 734b39a8ed alt_serdes: Fix some issues in the _hw.tcl script 2016-09-13 17:42:51 +03:00
Rejeesh Kutty cf9ac730a8 pzsdr1- new rev. board delays 2016-09-13 10:32:13 -04:00
Istvan Csomortani 9a2d2e8a02 version_upgrade: Update FMCADC4 to 2016.2 2016-09-13 15:04:11 +03:00
Rejeesh Kutty bced17a16f axi_ad9144- qsys updates 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 01b7662e05 axi_ad9680- qsys updates 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 236a938425 daq2/a10gx- qsys updates 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 5df30ac6b0 daq2/a10gx- xcvr sharing 2016-09-12 14:57:50 -04:00
Rejeesh Kutty c6998dd396 scripts- altera conduit 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 73ebf1225c axi_adxcvr- ip/phy split 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 21545ee83f avl_adxcvr- ip/phy split 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 8718b7f477 avl_adxphy- ip/phy split 2016-09-12 14:57:50 -04:00
Rejeesh Kutty d30ffdb7e9 avl_adxcfg- ip/phy split 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 9159e31244 axi_adxcvr- compile fixes 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 5a309d8863 avl_adxphy- split 2016-09-12 14:57:50 -04:00
Rejeesh Kutty 2a34f9baa8 alt-serdes, in & out 2016-09-12 11:45:23 -04:00
Rejeesh Kutty 9e0c39a71b alt_serdes_clk- changes 2016-09-12 10:30:28 -04:00
Istvan Csomortani f4be0524b4 altera/common: Add SERDES related modules 2016-09-09 18:04:41 +03:00
Istvan Csomortani a183e51a12 axi_ad9361: Add parameter R1_MODE_EN 
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
 2016-09-09 16:34:11 +03:00
Istvan Csomortani e42206e510 axi_ad9361: Add a TDD enable/disable parameter 2016-09-09 14:38:28 +03:00
Istvan Csomortani be41a8bcaa axi_ad9361: Delete debug ports of the tdd module 2016-09-09 14:38:28 +03:00
Adrian Costina 521c41ce32 adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier 2016-09-08 11:44:45 +03:00
Adrian Costina 40c9fc92c1 a10soc: Switched to tcl flow 2016-09-08 11:31:06 +03:00
Adrian Costina 0d095f5da9 a10gx: Added system_type variable in common design 2016-09-08 11:29:14 +03:00
Istvan Csomortani bae63ae5b1 version_upgrade: Update the DAQ3 project to 2016.2 2016-09-06 11:41:37 +03:00
Istvan Csomortani b8c34791d5 version_upgrade: fmcjesdadc1 updated to 2016.2 
Xilinx IP core JESD204 is updated to version 7.0
 2016-09-06 11:41:37 +03:00
AndreiGrozav b837883b98 pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection 2016-09-01 17:16:59 +03:00
AndreiGrozav bbcf2a3ec3 axi_ad9434/axi_ad9434_constr: Change constraint file to resolve critical warning 2016-09-01 17:16:59 +03:00
Rejeesh Kutty 4ae084ee32 avl_adxcvr- compile fixes 2016-09-01 10:06:28 -04:00
Rejeesh Kutty 5544e3cf10 axi_adxcvr- compile fixes 2016-09-01 10:06:28 -04:00
Rejeesh Kutty 230f1526c0 avl_adxcfg- compile fixes 2016-09-01 10:06:28 -04:00
AndreiGrozav 93fa5aeec3 fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2 2016-09-01 16:11:39 +03:00
Adrian Costina dc21384002 pzsdr: Update ccpci base design 2016-09-01 09:06:30 +03:00