4a5b7fc723
scripts- reconnect added
2016-09-29 11:50:58 -04:00
e40311eee9
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
2016-09-29 09:14:37 +01:00
4239f64125
dacfifo- board pin warnings
2016-09-27 14:49:20 -04:00
751a66eb72
plddr3/zc706- board pin warning
2016-09-26 15:20:37 -04:00
79b9e21be8
board- xcvr procedure
2016-09-26 15:20:18 -04:00
8314efd4e9
fmcomms11- xcvr updates
2016-09-26 15:19:29 -04:00
7fd9280cbf
fmcomms11- xcvr updates
2016-09-26 15:19:05 -04:00
f5809b8817
adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port
2016-09-24 10:09:05 +03:00
2d307d5f58
a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design
2016-09-24 10:06:35 +03:00
df37a23a48
pzsdr/ccfmc- rgmii critical warnings fix
2016-09-22 11:38:43 -04:00
dc6f7bbc4e
pzsdr/ccfmc - loopback updates
2016-09-22 11:18:13 -04:00
0e2572bbd8
pzsdr- ccbrk_cmos- loopback changes
2016-09-21 13:16:04 -04:00
14ad1ea741
pzsdr- swap clear-up
2016-09-21 13:15:40 -04:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
143423e3b9
adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera
2016-09-21 18:13:02 +03:00
500d8bfb90
adrv9371x: A10GX, fix makefile and system_qsys.tcl script
2016-09-21 18:11:35 +03:00
79f34c9de7
ccbrk- test updates
2016-09-21 11:04:22 -04:00
a2e60cf693
ccbrk - test
2016-09-21 11:04:22 -04:00
3ca9fe0919
sdrstk- remove critical warnings from ps7
2016-09-16 14:06:12 -04:00
f1e787f86b
fmcomms2: TDD control is enabled by default
2016-09-16 14:45:39 +03:00
2a7bc31c01
pzsdr1- disable gpreg constraints
2016-09-15 13:49:04 -04:00
67d4e71ff0
pzsdr1- disable gpreg constraints
2016-09-15 12:41:40 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
631923e9f0
usb_fx3: Update to Vivado 2016.2
2016-09-14 15:41:27 +03:00
9118ca3986
version_upgrade: Update MOTCON2 to 2016.2
2016-09-14 10:58:06 +03:00
cf9ac730a8
pzsdr1- new rev. board delays
2016-09-13 10:32:13 -04:00
9a2d2e8a02
version_upgrade: Update FMCADC4 to 2016.2
2016-09-13 15:04:11 +03:00
236a938425
daq2/a10gx- qsys updates
2016-09-12 14:57:50 -04:00
5df30ac6b0
daq2/a10gx- xcvr sharing
2016-09-12 14:57:50 -04:00
521c41ce32
adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
2016-09-08 11:44:45 +03:00
40c9fc92c1
a10soc: Switched to tcl flow
2016-09-08 11:31:06 +03:00
0d095f5da9
a10gx: Added system_type variable in common design
2016-09-08 11:29:14 +03:00
bae63ae5b1
version_upgrade: Update the DAQ3 project to 2016.2
2016-09-06 11:41:37 +03:00
b8c34791d5
version_upgrade: fmcjesdadc1 updated to 2016.2
...
Xilinx IP core JESD204 is updated to version 7.0
2016-09-06 11:41:37 +03:00
b837883b98
pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection
2016-09-01 17:16:59 +03:00
93fa5aeec3
fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
2016-09-01 16:11:39 +03:00
dc21384002
pzsdr: Update ccpci base design
2016-09-01 09:06:30 +03:00
2f9ac4a342
altera- qsys-script does not support most tcl commands
2016-08-30 11:50:36 -04:00
917da79da1
altera- source defaults for qsys-script
2016-08-30 11:50:36 -04:00
8192e755e1
altera- defaults
2016-08-30 11:50:36 -04:00
1eccf5af07
fmcomms7: Update common design to Vivado 2016.2
2016-08-30 16:46:15 +03:00
2015bcedaa
fmcadc2: Update common design to Vivado 2016.2
2016-08-30 16:42:58 +03:00
6f0d124861
fmcadc5: Update to Vivado 2016.2
2016-08-30 16:09:28 +03:00
4248b9373a
ad6676evb: Update to Vivado 2016.2
2016-08-30 16:08:07 +03:00
a6e6b3f96e
version_upgrade: Update fmcomms1 common design to Vivado 2016.2
2016-08-29 15:59:15 +03:00
2e59f377e1
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
2016-08-29 09:50:46 +03:00
271029768c
pzsdr/cmos - swap==1
2016-08-26 10:31:00 -04:00
d18f6aa816
adrv9371x: A10GX, added adcfifo
...
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
5cc2ab37a5
version_upgrade: Common ZC702 get an upgrade to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 10:20:04 +03:00
cd0c981b50
projects/scripts: Fix to prevent a warning
...
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
2016-08-26 10:08:00 +03:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
AndreiGrozav