e736504e0f
fmcjesdadc1, usdrx1: Using the same clock in rx_data path
2017-03-10 14:26:51 +02:00
d08d1d5a1b
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
2017-03-10 14:20:42 +02:00
452e5e5ce0
fmcomms2- add delay reporting for iodelay
2017-03-09 15:29:15 -05:00
8bdfbe2b0a
fmcomms2- report delays
2017-03-09 15:21:42 -05:00
ce6b0cc7f3
util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
...
This removes the added DC component that was introduced by the previous rounding mode
2017-03-09 16:33:17 +02:00
7e5d8664ad
fmcjesdadc1_a5gt: rx_data pins are all associated to the same clock
2017-03-09 08:57:03 +02:00
0e002f2f31
daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-09 08:50:55 +02:00
eb946b54cc
util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input
2017-03-08 14:29:26 +02:00
660dddf1e8
util_dacfifo: Define constraints for bypass
2017-03-07 16:14:46 +02:00
191669ad28
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 16:13:46 +02:00
fc8af6903f
pzsdr2/ccfmc- add rf input protection
2017-03-06 16:19:55 -05:00
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
38a27d02f6
a10soc/plddr4- differential refclk
2017-03-06 14:11:36 -05:00
936c441763
adrv9371x- dacfifo bypass-gpio control
2017-03-06 10:35:09 -05:00
762276a880
adrv9371x- dacfifo changes
2017-03-06 10:33:52 -05:00
7559d23873
util_dacfifo/constraints- false paths for bypass
2017-03-06 10:33:07 -05:00
4a6fe54fcf
daq2_common: Update common scripts
...
Add new port connection for util_dacfifo
2017-03-03 18:49:10 +02:00
7478777d8d
axi_dacfifo: Match the ports with util_dacfifo
2017-03-03 18:46:16 +02:00
760228d676
util_dacfifo: Update the util_dacfifo
...
Fix bypass and undate the general functionality. If bypass enabled
the FIFO will function as a normal CDC FIFO.
2017-03-03 18:43:36 +02:00
e0d4607692
adcfifo- asym_mem primitive changes
2017-03-01 15:55:56 -05:00
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
3586397f57
altera/common- add asymmetric fifo
2017-03-01 15:35:04 -05:00
bc6a09c828
adrv9371x/a10soc- dacfifo added
2017-03-01 15:35:04 -05:00
5b5c0dde99
ad6676evb: Set default xcvr parameters to common design
2017-03-01 11:32:17 +02:00
b78e9d8c27
daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
0cc5130c9a
adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
c1be17a3af
Altera a10 devices: disable warnings regarding unused channels
2017-03-01 11:32:17 +02:00
dc168f41fe
adrv9371_a10soc: Fixed port assignments
2017-03-01 11:32:17 +02:00
aad41039bd
a10soc- plddr4 settings
2017-02-28 13:36:28 -05:00
9c65166e26
ad9371- missing net declarations
2017-02-28 13:31:23 -05:00
104e9dfcdc
adc/dac-fifo altera cores
2017-02-28 13:30:50 -05:00
59dda01419
m2k: Disabled DDS cores for the generic project
2017-02-28 10:10:28 +02:00
0d231935ef
library/util_dacfifo- match bypass port with axi_dacfifo
2017-02-27 16:06:39 -05:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
19c7b5d340
fmcadc5- move adc fifo settings to system-board
2017-02-27 16:06:39 -05:00
c1aac4a9fb
common: adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
1d6ddacfd6
axi_ip_constr: Fix constraints
...
The filter for CDC registers were too generic, and a few non-CDC
register were set as asynchronous register.
2017-02-27 16:25:09 +02:00
1c8e63cb68
axi_adc_trigger: Added triggered register
2017-02-27 14:26:19 +02:00
37a1c98c12
axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching
2017-02-27 14:19:54 +02:00
545e458997
m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage
2017-02-27 14:17:29 +02:00
eda585f0e4
m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2
2017-02-27 14:16:32 +02:00
908da60ab6
m2k: zed, changed constraints so they are the same with the ZED default configuration
...
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
2017-02-27 14:13:34 +02:00
0059c907ea
adrv9371: Drive the TX DMA interface with sys_dma_clk
2017-02-24 15:50:12 +02:00
11623e79be
axi_dacfifo: Fix clock for read address generation
2017-02-24 15:47:04 +02:00
3e596347fd
axi_dacfifo: Delete unused wires
2017-02-24 15:45:51 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
f326c03ff3
axi_dacfifo: Define constraint for bypass
...
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-02-24 12:35:42 +02:00
b9d3039568
axi_dacfifo: Register the dac_valid signals
2017-02-24 12:34:58 +02:00
debc6e2066
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-02-24 12:32:25 +02:00
AndreiGrozav
Rejeesh Kutty
Adrian Costina
Istvan Csomortani