Istvan Csomortani
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7be017baa3
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daq1: Add AXI PLDDR FIFO to the receive path
The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
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2016-07-07 07:15:54 +03:00 |
Rejeesh Kutty
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697469ee28
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daq1- updates
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2016-03-15 12:39:38 -04:00 |
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Istvan Csomortani
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8c69c9d2ce
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daq1_zc706 : Update the project
+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
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2016-01-19 11:20:35 +02:00 |
|
Rejeesh Kutty
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a6cae6b477
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iobuf: do is a system verilog keyword
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2015-05-21 14:06:17 -04:00 |
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Istvan Csomortani
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75d2c7e93e
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daq1_zc706: Update project to the new framework
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2015-03-24 12:45:24 +02:00 |
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Istvan Csomortani
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0ecfc14e95
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daq1_fmc: Update interrupts.
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2014-11-24 18:23:32 +02:00 |
|
Istvan Csomortani
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9b104f1657
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daq1_fmc: Get rid of the concat module inside the block design.
xl_concat just causing troubles, no need to use it, if not justified.
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2014-11-24 18:23:30 +02:00 |
|
Rejeesh Kutty
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577441bd0c
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daq1: clean up dma interfaces
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2014-09-23 14:23:41 -04:00 |
|
Istvan Csomortani
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ee752ec08a
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daq1: Initial commit
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2014-09-01 18:34:31 +03:00 |