Commit Graph

97 Commits (489b31e929e656ded4d6f394bdc0cd920327629d)

Author SHA1 Message Date
Adrian Costina 43946a54a4 axi_dmac: Added C_FIFO_SIZE parameter 2015-07-24 15:30:10 +03:00
Adrian Costina f7d28e0944 axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them 2015-07-23 17:01:02 +03:00
Lars-Peter Clausen c372064302 Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Rejeesh Kutty aa24c442f5 a10gx- no-ddr 2015-06-01 11:00:01 -04:00
Rejeesh Kutty d7b68c39ef altera- sdc 2015-06-01 10:59:59 -04:00
Rejeesh Kutty 2a0bdbebf2 altera- sdc 2015-06-01 10:59:58 -04:00
Rejeesh Kutty 5c6340e927 dmac: clock-typo 2015-05-21 14:06:11 -04:00
Rejeesh Kutty da0409b5a6 library- qsys components 2015-05-20 11:51:50 -04:00
Adrian Costina c9c05e21c2 axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis 2015-05-13 16:34:06 +03:00
Istvan Csomortani 0613dca0b7 axi_dmac: Move the 'axis_xlast' logic into the dest_axi_stream module 2015-05-06 16:10:28 +03:00
Adrian Costina 949abcdc8f Makefile: Updated makefiles so that the project recipe does not depend on lib 2015-05-06 14:58:29 +03:00
Istvan Csomortani 65af205d6b axi_dmac: Add axis_last control signal to the Master AXI Streaming interface
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
2015-05-06 13:54:31 +03:00
Lars-Peter Clausen 7b073aaec1 axi_dmac: Always generate local interrupt for asynchronous interfaces
While the reset for the memory mapped AXI master is synchronous to some
clock it is not necessarily synchronous to the clock used for that
interface. So always generate a local reset signal to avoid problems that
could result from this.

While we are at it also update the code to only generate a local reset if
the interface is asynchronous to the register map, otherwise use the
register map reset.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-22 13:22:23 +02:00
Lars-Peter Clausen 5edcc753ec axi_dmac: Ignore timing on more debug signals
Ignore the timing path from the current DMA address to the register map,
this is just a debug signal at the moment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-22 13:22:23 +02:00
Lars-Peter Clausen ae808ba942 axi_dmac: Fix block ram constraint
If the internal FIFO is larger than one block ram there will be multiple
BRAMs called ram_reg[0], ram_reg[1]. Modify the BRAM constraint rule so that
it matches these as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 19:56:42 +02:00
Lars-Peter Clausen 0dc3bb8905 axi_dmac: Fix src_reponse_fifo control signals
The src_response_fifo has been removed from the design, but we still need to
assert the ready and empty control signals for things to work properly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
Lars-Peter Clausen 42a9da0659 axi_dmac: Only apply CDC constraints if clocks are asynchronous
We really only want to apply the CDC constraints if the clocks are actually
asynchronous. Unfortunately we can't use if ... inside a xdc script. But we
can use expr which has support for a ? b : c if-like expression. We can use
that to create helper variables that contains valid clock when the clock
domains are asynchronous or {} if they are not. Passing {} as
set_false_path/set_max_delay as either the source or destination will cause
it to abort and no constraints will be added.

Also add -quiet parameters to avoid generating warning if the constraints
could not be added.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 17:20:25 +02:00
Lars-Peter Clausen 9c249d25ab axi_dmac: Make internal resets active high
All the FPGA internal control signals are active high, using a active low
reset inserts a extra invert LUT. By using a active high reset we can avoid
that.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 17:20:25 +02:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina fd2f5836f0 axi_dmac: Fixed type in the altera hardware file 2015-04-17 14:59:47 +03:00
Adrian Costina 374f82e7de makefiles: The clean command for library won't remove the xml files, except for component.xml.
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Lars-Peter Clausen f13666cd81 ad9361: axi_dmac_constr: Fix typo 2015-04-16 10:01:19 +02:00
Lars-Peter Clausen f51c941c2d axi_dmac: Set proper constraints
Instead of just marking all clock domains as asynchronous set the
appropriate constraints for each CDC path.

For single-bit synchronizers use set_false_path to not constraint the path
at at all.

For multi-bit synchronizers as used for gray counters use set_max_delay with
the source clock period domain to make sure that the signal skew will not
exceed one clock period. Otherwise one bit might overtake another and the
synchronizer no longer works correctly.

For multi-bit synchronizers implemented with hold registers use
set_max_delay with the target clock period to make sure that the skew does
not get to large, otherwise we might violate setup and hold time.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:26 +02:00
Lars-Peter Clausen 24df683a2a axi_dmac: Disable src_response_fifo for now
The result of the src_response_fifo is currently not used so disable it for
now.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:12 +02:00
Lars-Peter Clausen f6594e276e Bring back AXIS FIFO as a separate module
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:06 +02:00
Adrian Costina 95e41e50a6 axi_dmac: Make all clocks asynchronous 2015-04-11 12:04:55 +03:00
Adrian Costina e9bd4b3512 axi_dmac: Updated altera core dependency, changed fifo files location 2015-04-09 17:58:21 +03:00
Lars-Peter Clausen b6458f9aab axi_dmac: Move axi_repack block to its own module
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.

Also rename it to util_axis_resize to better reflect its function.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
Lars-Peter Clausen bdaad46704 axi_dmac: Remove up_write signal
up_write is just an alias for up_wreq these days. Just always use the later
and remove the former.
2015-04-08 14:43:56 +02:00
Lars-Peter Clausen 6ba0667939 axi_dmac: Add fifo_wr/fifo_rd interfaces
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen d17cd22ef1 adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus()
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.

This makes the function more flexible and e.g. allows to handle buses from other vendors.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Rejeesh Kutty 7224ca1f0c dma: moved 2015-04-07 15:35:47 -04:00
Rejeesh Kutty 8af60576cd dma: constraints 2015-04-06 13:38:31 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty 5a5ffb7745 makefile: added 2015-04-01 16:27:51 -04:00
Lars-Peter Clausen fd7a423f74 axi_dmac: Reset data stream resize blocks when disabled
When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.

To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:18:34 +02:00
Adrian Costina 4b1d9fc86b axi_dmac: Modified in order to avoid vivado crash 2015-04-01 11:39:25 +03:00
Istvan Csomortani 0e1a60e8b7 axi_dmac: Brought up the transfer request signal for the dest_fifo and dest_axi_stream interface. 2015-03-26 12:20:32 +02:00
Lars-Peter Clausen 65bda6505e axi_dmac: Correctly handle shutdown for the request splitter
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen 731e1c0996 axi_dmac: Use internal enable signal for the request generator
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen 582ea06918 axi_dmac: request_generator: Stop generating requests when disabled
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.

So just stop generating burst requests once the DMAC is being disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen aa594e15f3 axi_dmac: fifo_inf: Handle overflow and underflow correctly
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:21 +01:00
Istvan Csomortani 96899313d8 axi_dmac: Fix constraint
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
Istvan Csomortani b10ba49425 axi_dmac: Fix constraint related issue
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
2015-01-23 18:44:17 +02:00
Istvan Csomortani d5bd485624 axi_dmac: Fix eot issue under 2014.4
Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
2015-01-23 18:39:33 +02:00
Lars-Peter Clausen f9628262aa axi_dmac: Add xfer_req signal to the streamin AXI source interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
Adrian Costina 121a416916 axi_dmac: Fixed constraints for axi_dmac core 2014-10-22 13:07:55 +03:00
Lars-Peter Clausen 22169c4a9c axi_dmac: Add default driver values for optional input ports
This silences warnings from the tools about undriven ports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:46 +03:00
Lars-Peter Clausen e7dbdff60c axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1
The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:41 +03:00