74b922f9f8
axi_*: Infer clock and reset signals of an IP
...
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.
The following IPs tcl script was updated:
- axi_ad9434
- axi_hdmi_tx
- util_cpack
- util_adxcvr
- axi_ad6676
- axi_ad9625
- axi_ad9379
- axi_ad9265
- util_tdd_sync
- util_rfifo
- util_wfifo
- axi_ad9361
- axi_ad9467
- util_upack
- axi_dacfifo
- axi_ad9152
- axi_ad9680
- util_clkdiv
- axi_ad9122
- axi_ad9684
- axi_mc_speed
- axi_mc_current_monitor
- axi_mc_controller
- util_gmii_to_rgmii
- util_adxcvr
- axi_ad9379
- axi_hdmi
- library
- axi_fmcadc5_sync
- util_adcfifo
- util_mfifo
- axi_jesd204_rx
- axi_jesd204_tx
- axi_ad9361
- axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
d840baee28
util_clkdiv: Register output port as a clock ( #33 )
...
If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:52:43 +01:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
c637d848bb
util_clkdiv: constraints should be applied LATE for this core
2017-04-03 18:14:29 +03:00
61afd106b5
util_clkdiv: Keep as valid only settings common for 7Series and Ultrascale
2017-01-18 11:56:24 +02:00
61ee24f26a
util_clkdiv: Make the clock division parametrizable and changed C_SIM_DEVICE to SIM_DEVICE
2017-01-16 14:37:26 +02:00
4b2602437f
util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching
2017-01-13 13:54:07 +02:00
9b29941c77
util_clkdiv: Add constraint file
2017-01-11 18:11:53 +02:00
609b01f9e4
util_clkdiv: Added division by 2 option
2016-11-24 16:01:37 +02:00
c072c2f89a
util_clkdiv: Add IP
2016-09-30 17:13:51 +03:00
Adrian Costina
Matthew Fornero
Istvan Csomortani