Commit Graph

4737 Commits (472b12feb73e981a827890f59f7d9b0f8fa41ba6)

Author SHA1 Message Date
Istvan Csomortani 472b12feb7 ad_rst: Update the reset synchronizer module
For a proper reset synchronization, the asynchronous reset signal should
be connected to the reset pins of the two synchronizer flop, and the
data input of the first flop should be connected to VCC.

In the first stage  we're synchronizing just the reset de-assertion, avoiding
the scenario when different parts of the design are reseting at different time,
causing unwanted behaviours.

In the second stage we're synchronizing the reset assertion.

The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW
(rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.
2018-08-06 21:24:41 +03:00
AndreiGrozav 22ac59c4cf scripts/adi_project.tcl: Overrides the default individual msg limit to 2000 2018-08-06 18:18:13 +03:00
Istvan Csomortani c152b60137 ad_mem_asym: Improve the implementation of the asymmetric RAM
Because the read interface got a read enable port too, update all the
ad_mem_asym instances.
2018-08-06 17:29:05 +03:00
Istvan Csomortani e092149cbc adi_ip: Use 'associate_bus_interface' command to setup the clock and reset for s_axi 2018-08-06 10:14:48 +03:00
Istvan Csomortani 9441f00f5f adi_ip: Define the default driver value to 0 for unused ports 2018-08-06 10:14:48 +03:00
Istvan Csomortani 1388554faa adi_board.tcl: Update the VCC/GND instance generation
Just one VCC or GND xlconstant will be generated for each width. This
way we can avoid having a lot of xlconstant instances with the same
configuration.
2018-08-06 10:14:14 +03:00
Laszlo Nagy 085c0ed0da fmcadc5: remove SYSREF from IOB
The SYSREF for RX is generated internally,
disable the IOB attribute from it to avoid critical warnings.
2018-07-26 12:33:25 +03:00
Lars-Peter Clausen d5a1aa81e8 jesd204: Check lane error count in register map testbench
Assign a unique value to each lane's error count register and verify that
the correct value is returned for the right lane.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-24 15:20:28 +02:00
Lars-Peter Clausen b2ed915fbc jesd204: Fix RX regmap testbench version ID
The RX register map testbench currently fails because the expected value
for the version register was not updated, when the version was incremented.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-24 15:20:28 +02:00
Lars-Peter Clausen 57a5baad33 jesd204: Fix loopback testbench
The loopback testbench currently fails, because the cfg_links_disable signal is not connected to the RX side of the link.

Fix this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-24 15:20:28 +02:00
AndreiGrozav 74288cf9cb axi_hdmi_tx: Added INTERFACE parameter for selecting the interface type
Update all carriers/projects bd for configurable video interface:
- common zc702, zc706, zed
- adrv9361z7035/ccfmc_lvds
- imageon
2018-07-24 15:56:22 +03:00
Laszlo Nagy 0caea39bad jesd204_rx/tx: make SYSREF IOB placement optional
In case when the SYSREF is connected to an FPGA IO which has a limitation
on the IOB register IN_FF clock line and the required ref clock is high
we can't use the IOB registers.
e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz;

If IOB is used in this case a pulse width violation is reported.

This change makes the IOB placement selectable in such case or
for targets which don't require class 1 operation.
2018-07-24 09:16:24 +03:00
Laszlo Nagy 4d8008e64c axi_dmac: fix address width detection
The round function from tcl is a rounding to nearest. Using it in address
width calculation produces incorrect values.
e.g.
 round(log(0xAF000000)/log(2)) will produce 31 instead of 32

The fix is to replace the rounding function with ceiling that guarantees
rounding up.
2018-07-20 18:12:24 +03:00
AndreiGrozav 235636a337 fmcomms5_zc702: Enable AXI_SLICE for the DMA
This will increase the timing margin for the design
2018-07-18 18:19:30 +03:00
AndreiGrozav 77db4c200c axi_ad9371: Increase dds quality 2018-07-18 18:19:30 +03:00
AndreiGrozav 89692b40b5 axi_ad9144: Increase dds quality 2018-07-18 18:19:30 +03:00
AndreiGrozav 989fa6fd27 axi_ad9122: Increase dds quality 2018-07-18 18:19:30 +03:00
AndreiGrozav 6083d74857 axi_ad9739a: Use polynomial DDS 2018-07-18 18:19:30 +03:00
AndreiGrozav 79003c53db ad_dds: Fix synthesis updates
- remove reset logic
- add wait for dac valid logic
- rewrite sine concatenation on wires for different path width to
suppress warnings
- use computed atan LUT tables
2018-07-18 18:19:30 +03:00
AndreiGrozav 892febe68a ad_dds_2: Remove unused disable logic feature 2018-07-18 18:19:30 +03:00
AndreiGrozav 8a306ce96b axi_ad9162: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 8cd88150f1 axi_ad9152: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav a2d3c87aa5 axi_adrv9009: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 92f0e809b5 jesd204/ad_ip_jesd204_tpl_dac: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 528460371c axi_ad9963: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 92dbd75414 axi_ad9739a: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 25dbca7eed axi_ad9371: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 42abe0cf46 axi_ad9361: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav d27ed93594 axi_ad9144: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 4a73e32941 axi_ad9122: Updates for ad_dds phase accumulator wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav a7f5746afb ad_dds: Add selectable phase width option. 2018-07-18 18:19:30 +03:00
AndreiGrozav 7b553997ab Add ad_dds.v
It will act as a wrapper for the previous dds modules(phase to angle conv.)
this module will furthermore contain the phase accumulator logic.
2018-07-18 18:19:30 +03:00
AndreiGrozav 35e8454fe7 Rename ad_dds.v to ad_dds_2.v 2018-07-18 18:19:30 +03:00
AndreiGrozav ad7e95b169 ad_dds: Add selectable out data width and fair rounding
The CORDIC has a selectable width range for phase and data of 8-24.
Regarding the width of phase and data, the wider they are the smaller
the precision loss when shifting but with the cost of more FPGA
utilization. The user must decide between precision and utilization.

The DDS_WD parameter is independent of CORDIC(CORDIC_DW) or
Polynomial(16bit), letting the user chose the output width.
Here we encounter two scenarios:
 * DDS_DW < DDS data width - in this case, a fair rounding will be
implemented corresponding to the truncated bits
 * DDS_DW > DDS data width - DDS out data left shift to get the
corresponding concatenation bits.
2018-07-18 18:19:30 +03:00
AndreiGrozav 2c1f9193cf ad_dds_1.v: Fully use the selectable data width feature
Update for the parametrized ad_mul module. This will scale
a selectable sine width in a multiplication module.
Rename the data and phase width parameters for legibility.
2018-07-18 18:19:30 +03:00
AndreiGrozav 568f2e180f ad_mul.v: Add parameters for A and B input widths
The out width will be A + B.
This change is backward compatible and it applies to both Altera and Xilinx.
2018-07-18 18:19:30 +03:00
AndreiGrozav 3dc7be3eab ad_dds_sine_cordic: Fix sine pic to pic amplitude.
When the tool calculates the X value for different phase widths, we
get rounding errors for every width in the interval [8;24].
Depending on the width thess errors cause overflows or smaller amplitudes
of the sine waves.
The error is not linear nor proportional with the phase. To fix the issue
a simple aproximation was chosen.
2018-07-18 18:19:30 +03:00
AndreiGrozav 6a1853654a ad_dds: Separated phase width from data width 2018-07-18 18:19:30 +03:00
AndreiGrozav 664c46eb72 ad_dds_sine_cordic: Ajust for rounding errors
And fix comment typo
2018-07-18 18:19:30 +03:00
AndreiGrozav c6173023f8 ad_dds_cordic: Move the shifting operation
Perform the shifting operation before addition/subtraction in a
rotation stage. In the previous method, the result of the arithmetic
operation was shifted and the outcome was presented to the next stage.
In this way, data connections will be reduced between pipeline stages
2018-07-18 18:19:30 +03:00
AndreiGrozav a96d9bd3c2 ad_dds_sine: Cosmetic updates only 2018-07-18 18:19:30 +03:00
AndreiGrozav 43f460e744 ad_dds_cordic_pipe.v: Optimize for implementation
The present changes make better use of the Carry Chain blocks resulting in
fewer FPGA resources being used.
2018-07-18 18:19:30 +03:00
AndreiGrozav dc80048733 ad_dds_sine_cordic.v: Suppress warning
Width mismatch warning from 32 to dynamic width.
2018-07-18 18:19:30 +03:00
AndreiGrozav ad425dee5f ad_dds_1.v: Fix concatenation width mismatch 2018-07-18 18:19:30 +03:00
AndreiGrozav 74a24c4edd fmcomms2/common: Use DDS cordic on 14 bit atan LUT 2018-07-18 18:19:30 +03:00
AndreiGrozav 3b319faef2 axi_ad9963:: Update for CORDIC algorithm
Add the new files to the IP list
Propagate DDS parameters to top file
2018-07-18 18:19:30 +03:00
AndreiGrozav 6f2d18692c axi_ad9739a: Update for CORDIC algorithm
Add the new files to the IP list
Propagate DDS parameters to top file
2018-07-18 18:19:30 +03:00
AndreiGrozav 74609d8fec axi_ad9379: Update for CORDIC algorithm
Add the new files to the IP list
Propagate DDS parameters to top file
2018-07-18 18:19:30 +03:00
AndreiGrozav 2ce10f4504 axi_ad9371: Update for CORDIC algorithm
Add the new files to the IP list
Propagate DDS parameters to top file
2018-07-18 18:19:30 +03:00
AndreiGrozav ca81397410 axi_ad9361: : Update for CORDIC algorithm
Add the new files to the IP list
Propagate DDS parameters to top file
2018-07-18 18:19:30 +03:00