AndreiGrozav
|
c21c6813a5
|
arradio c5soc: Update project to tcl flow.
-Update to tcl flow
-Add missing i2c interface
|
2017-06-23 15:53:43 +03:00 |
Rejeesh Kutty
|
3c49470e08
|
arradio/c5soc- qsys-script flow
|
2017-06-22 15:25:20 +03:00 |
|
Rejeesh Kutty
|
2554677123
|
arradio/c5soc- remove qsys files
|
2017-06-21 17:40:37 +03:00 |
|
Rejeesh Kutty
|
4ccaeffc8f
|
arradio/c5soc- updated to new framework/16.0
|
2017-06-21 17:39:55 +03:00 |
Istvan Csomortani
|
b30041f7f3
|
axi_dacfifo: Redesign the bypass functionality
|
2017-04-03 10:37:08 +03:00 |
|
Rejeesh Kutty
|
a15e05c497
|
adcfifo- remove axi-byte-width parameter
|
2017-02-17 15:29:10 -05:00 |
|
Rejeesh Kutty
|
cb3d1883bc
|
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
|
2017-02-17 15:21:33 -05:00 |
|
Istvan Csomortani
|
95a4ea20c8
|
axi_dacfifo: Delete redundant parameter BYPASS_EN
|
2017-02-16 19:53:44 +02:00 |
|
Rejeesh Kutty
|
c39ed08edd
|
zcu102/*- actual clock == desired clock
|
2017-02-06 12:53:47 -05:00 |
|
Rejeesh Kutty
|
be1328c55b
|
kcu105- added missing ethernet configurations
|
2017-01-23 10:14:09 -05:00 |
|
Rejeesh Kutty
|
18660c7ab4
|
fmcjesdadc1/a5gt: ddr3 use ip constraints
|
2016-12-22 14:14:21 -05:00 |
|
Rejeesh Kutty
|
1ceec2e2a9
|
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
|
2016-12-22 14:14:21 -05:00 |
|
Rejeesh Kutty
|
eba30b0cde
|
projects/altera- qii_auto_pack option
|
2016-12-22 14:14:21 -05:00 |
|
Rejeesh Kutty
|
4a783d523d
|
projects/altera* - default & common qsys commands
|
2016-12-20 16:27:44 -05:00 |
Adrian Costina
|
9fb7db97da
|
a5gte: Fixed timing violations
|
2016-12-13 10:30:24 +02:00 |
|
Adrian Costina
|
8ebc8fe4e2
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
|
AndreiGrozav
|
8e69c838e1
|
common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
|
2016-12-09 13:54:39 +02:00 |
|
Rejeesh Kutty
|
fb287d0178
|
kcu105- updates to match xilinx trd
|
2016-12-08 09:32:33 -05:00 |
|
Rejeesh Kutty
|
4739d05269
|
zc706pr/common- removed
|
2016-11-18 14:52:39 -05:00 |
|
Rejeesh Kutty
|
f43248c2bc
|
common/pzsdr*- removed
|
2016-11-18 11:32:43 -05:00 |
|
Rejeesh Kutty
|
959055bd54
|
common/a5gt- updates
|
2016-11-10 16:56:35 -05:00 |
|
Rejeesh Kutty
|
c6730ab2d7
|
fmcjesdadc1/a5gt- updates
|
2016-11-10 11:36:41 -05:00 |
|
Rejeesh Kutty
|
8af0731bb0
|
a5gt- qsys2tcl flow
|
2016-11-10 11:30:18 -05:00 |
|
Rejeesh Kutty
|
3cc416ca60
|
pzsdr1- fix typo on system_ps7
|
2016-11-09 12:04:30 -05:00 |
|
Rejeesh Kutty
|
f0af8216ce
|
common/a5soc- device can not run at 100M cpu clock
|
2016-11-08 15:19:23 -05:00 |
|
Rejeesh Kutty
|
d9cfccc05f
|
common/a5soc- gpio in/out separation
|
2016-11-08 15:19:02 -05:00 |
|
Rejeesh Kutty
|
6b492b79db
|
a10soc - remove default assignments
|
2016-11-04 15:01:19 -04:00 |
|
Rejeesh Kutty
|
8ea9beffaf
|
fmcjesdadc1- a5soc tcl updates
|
2016-11-04 15:01:19 -04:00 |
|
Rejeesh Kutty
|
4e99c3be9a
|
a5soc- tcl flow updates
|
2016-11-04 15:01:19 -04:00 |
|
Rejeesh Kutty
|
50552ce7d6
|
adrv9371x- altera updates
|
2016-10-27 09:25:00 -04:00 |
|
Rejeesh Kutty
|
f752f0c9d7
|
a10soc- xcvr updates
|
2016-10-27 09:25:00 -04:00 |
|
Rejeesh Kutty
|
cb97bc500a
|
hdlmake updates
|
2016-10-17 16:29:57 -04:00 |
|
Rejeesh Kutty
|
721ee98a06
|
zcu102- misc fixes
|
2016-10-06 10:18:14 -04:00 |
|
Rejeesh Kutty
|
baabe20766
|
common/zcu102- spi connections & clock
|
2016-10-05 14:01:59 -04:00 |
|
Rejeesh Kutty
|
9afff7ae60
|
common/zcu102- 2016.2 updates
|
2016-09-30 11:55:10 -04:00 |
|
Adrian Costina
|
e40311eee9
|
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
|
2016-09-29 09:14:37 +01:00 |
|
Rejeesh Kutty
|
4239f64125
|
dacfifo- board pin warnings
|
2016-09-27 14:49:20 -04:00 |
|
Rejeesh Kutty
|
751a66eb72
|
plddr3/zc706- board pin warning
|
2016-09-26 15:20:37 -04:00 |
|
Adrian Costina
|
2d307d5f58
|
a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design
|
2016-09-24 10:06:35 +03:00 |
|
Rejeesh Kutty
|
14ad1ea741
|
pzsdr- swap clear-up
|
2016-09-21 13:15:40 -04:00 |
|
Adrian Costina
|
143423e3b9
|
adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera
|
2016-09-21 18:13:02 +03:00 |
|
Rejeesh Kutty
|
cf9ac730a8
|
pzsdr1- new rev. board delays
|
2016-09-13 10:32:13 -04:00 |
|
Adrian Costina
|
40c9fc92c1
|
a10soc: Switched to tcl flow
|
2016-09-08 11:31:06 +03:00 |
|
Adrian Costina
|
0d095f5da9
|
a10gx: Added system_type variable in common design
|
2016-09-08 11:29:14 +03:00 |
|
AndreiGrozav
|
b837883b98
|
pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection
|
2016-09-01 17:16:59 +03:00 |
|
Rejeesh Kutty
|
917da79da1
|
altera- source defaults for qsys-script
|
2016-08-30 11:50:36 -04:00 |
|
Rejeesh Kutty
|
8192e755e1
|
altera- defaults
|
2016-08-30 11:50:36 -04:00 |
|
AndreiGrozav
|
2e59f377e1
|
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
|
2016-08-29 09:50:46 +03:00 |
|
Rejeesh Kutty
|
271029768c
|
pzsdr/cmos - swap==1
|
2016-08-26 10:31:00 -04:00 |
|
Istvan Csomortani
|
5cc2ab37a5
|
version_upgrade: Common ZC702 get an upgrade to 2016.2
Xilinx IP Clock Wizard updated to version 5.3
|
2016-08-26 10:20:04 +03:00 |