Commit Graph

3921 Commits (41d305b6b6a61ae4b6266264d351dc1befdf97fa)

Author SHA1 Message Date
Adrian Costina 20672a3a8b mitx045: ip automatic version update 2017-04-14 17:46:25 +03:00
Adrian Costina 954037a716 microzed: ip automatic version update 2017-04-14 17:24:24 +03:00
Adrian Costina ebc04bcd9c usdrx1: ip automatic version update 2017-04-14 17:16:35 +03:00
Adrian Costina 24b797f1a6 motcon2: ip automatic version update 2017-04-14 17:11:08 +03:00
Adrian Costina 4981e6e525 usb_fx3: ip automatic version update 2017-04-14 16:55:30 +03:00
Adrian Costina c419b0042b pluto: ip automatic version update 2017-04-14 16:55:07 +03:00
Adrian Costina 79174422b6 imageon: ip automatic version update 2017-04-14 16:54:42 +03:00
Adrian Costina 4bda0c3a1a cftl_cip: ip automatic version update 2017-04-14 16:54:07 +03:00
Adrian Costina afe8b071a3 cftl_std: ip automatic version update 2017-04-14 16:53:10 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav 04a4001dba Ip automatic version update: fmcadc2, fmcadc5 2017-04-12 19:03:16 +03:00
AndreiGrozav 627f78ec19 Ip automatic version update: common/board
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
Istvan Csomortani 3f0633aadc spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:57:22 +02:00
Rejeesh Kutty 6d2b3bc1c7 adi_project- try something simple first 2017-04-11 14:27:35 -04:00
Rejeesh Kutty 1d9a8a24dc adi_board- create_bd_cell replacement 2017-04-11 14:26:02 -04:00
AndreiGrozav bc9483c5a2 Ip automatic version: Update ad*/common/ad*_bd.tcl
ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
Rejeesh Kutty 454e6c0382 daq2- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:53 -04:00
Rejeesh Kutty 2535165461 xilinx- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:19 -04:00
Rejeesh Kutty 80f93e6a31 zc706- ad-ip-instance & ad-ip-parameter 2017-04-06 13:03:22 -04:00
Rejeesh Kutty 820874ef93 adi_board- add auto ip version handling 2017-04-06 13:02:17 -04:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c637d848bb util_clkdiv: constraints should be applied LATE for this core 2017-04-03 18:14:29 +03:00
Istvan Csomortani e0efbe210e constraints: constraint files should be specified at adi_ip_files 2017-04-03 18:12:28 +03:00
Rejeesh Kutty 2f023437b4 adi_ip- remove adi_ip_constraints 2017-04-02 10:42:51 -04:00
Rejeesh Kutty d916697263 adi_ip- a little rearrangement 2017-04-01 09:04:35 -04:00
Istvan Csomortani fd56b5a6d3 axi_ad9122: Update constraint files 2017-03-31 10:13:42 +03:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Lars-Peter Clausen 495d2f3056 axi_dmac: Propagate awlen/arlen width through the core
Depending on whether the core is configured for AXI4 or AXI3 mode the width
of the awlen/arlen signal is either 8 or 4 bit. At the moment this is only
considered in top-level module and all other modules use 8 bit internally.
This causes warnings about truncated signals in AXI3 mode, to resolve this
forward the width of the signal through the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 17:19:38 +02:00
Istvan Csomortani ebfed4b24b ad_axi_ip_constr.xdc: Delete file 2017-03-30 16:16:02 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
2017-03-30 16:16:02 +03:00
Istvan Csomortani 31a5c674f2 fmcomms2: Update constraints file paths 2017-03-30 16:16:02 +03:00
Istvan Csomortani 8ba6012b6b restructure: Move xilinx specific constraints to /library/xilinx/common/ 2017-03-30 16:16:02 +03:00
Lars-Peter Clausen 983e56d72c ad9963: Remove localparams from module parameter list
Declaring local parameters in the module parameter list is not valid
verilog. For some reasons Vivado accepts it nevertheless so the code has
worked so far. But this is not true for other tools, so move the local
parameter definitions inside the module body.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:40:28 +02:00
Lars-Peter Clausen e04793b6eb m2k: standalone: Assign 0 to unused GPIO inputs
To avoid warnings from the tools assign 0 to the unused GPIO inputs.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:16:25 +02:00
Rejeesh Kutty 8eb1dd0a8b adrv9371x/altera- xilinx/chip-select consistency 2017-03-29 12:59:09 -04:00
Istvan Csomortani 1d448f0013 adi_ip: Set up SCOPE_TO_REF for xdc and save the core 2017-03-29 18:40:24 +03:00
Istvan Csomortani ea7e93d27f fmcomms2: Use the new constriants from 335fef0 2017-03-29 18:36:09 +03:00
Istvan Csomortani 335fef0f42 ad_axi_ip_constr: Split up this constraint file into separate files
For experimentation, to solve a constraint scoping issue, split up the
ad_axi_ip_constraint file into separate constraints file, in function
of there parent module.
2017-03-29 18:31:40 +03:00
Lars-Peter Clausen 24a7d8ea9d m2k: Remove redundant s_axi_{aclk,aresetn} assignment
ad_cpu_interconnect will make sure to connect the clock and the reset of
the AXI interface. Remove the redundant manual assignments.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-28 11:14:48 +02:00
Rejeesh Kutty deb8635854 adrv9371x/altera- gpio equivalency fix 2017-03-27 16:37:55 -04:00
Rejeesh Kutty 8f1564a9c4 adrv9371x/a10gx- gpio matching 2017-03-27 13:51:45 -04:00
Rejeesh Kutty 2419b3626b ad9684- fix sdc typo 2017-03-23 12:49:44 -04:00
Rejeesh Kutty ae0f4672b2 daq1/a10gx- fix project to compile 2017-03-23 09:46:40 -04:00
Rejeesh Kutty cc6bf53d98 adrv9371x/a10soc- altera reset synchronizer false path? 2017-03-23 09:46:40 -04:00
Adrian Costina 968d94603e fmcjesdadc1: Update xcvr configuration to the default one used for this board 2017-03-23 11:31:00 +02:00
Rejeesh Kutty 4a275302a0 a5soc- add ddr3 location assignments 2017-03-22 10:12:34 -04:00
Rejeesh Kutty 7e87ecae22 altera/a10gx- daq1/fmcomms2 fix typos 2017-03-22 09:48:02 -04:00
Rejeesh Kutty b3f06af77a altera srf files do not work 2017-03-22 09:25:50 -04:00
Rejeesh Kutty 66a5d44a18 a5gte- add constraints for tq 2017-03-21 10:53:31 -04:00
Rejeesh Kutty 2e22ce3b62 a10gx- ignore preliminary timing model warnings 2017-03-21 10:52:28 -04:00