d931b2ee64
ad9162 core verilog files
2016-06-30 10:24:01 -04:00
8d558b2538
make: Update Make files
2016-06-29 14:50:07 +03:00
18e28b01fd
axi_ad7616: Add burst counter to the parallel interface
...
With this counter the parallel logic supports the burst sequencer.
2016-06-29 14:17:28 +03:00
e6494b9a74
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 14:11:02 +03:00
64633e519c
Merge remote-tracking branch 'origin/dev_ad7616' into dev
2016-06-29 12:32:39 +03:00
cdf01a492e
library/axi_dacfifo: Update the bypass logic
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The bypass logic is located between the AXI read controller and the
DAC CDC fifo. When the bypass is enabled the DMAC destination interface
must be clocked with the PL_DDR controller's ui_clk. This way it can easily
switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 12:24:54 +03:00
def47dd536
interfaces: added xcvr interfaces
2016-06-17 12:00:15 -04:00
36fbf4fc42
util_adxcvr: shared xcvr cores
2016-06-17 11:59:42 -04:00
87cf13b0ef
util_adxcvr- system verilog interfaces
2016-06-16 16:41:43 -04:00
80ce7aeb66
util_adxcvr- updates
2016-06-16 16:40:57 -04:00
7c762f63a8
library/axi_dacfifo: Fix the control logic of the write side
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Fix the control logic for the AXI write transactions.
2016-06-15 13:49:00 +03:00
d5ce137c55
library/axi_dacfifo: Fix reset for a few registers
2016-06-15 13:49:00 +03:00
10090a296e
library/axi_dacfifo: Cosmetic changes
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Rename a few registers and improve consistency.
2016-06-15 13:49:00 +03:00
7485d27d37
ad9361/altera- device-family variable
2016-06-14 12:28:13 -04:00
5d437083cc
ad9361/altera- a10+ only
2016-06-14 12:19:54 -04:00
dc45287b14
util_adxcvr- added
2016-06-14 12:19:18 -04:00
c19ed4c8ef
axi_hdmi_tx_core: Fixed embedded sync synchronization signals
2016-06-14 14:30:28 +03:00
aee38e1cc9
up_hdmi_tx: Fixed data path width
2016-06-14 14:27:03 +03:00
27fd5f5bdc
modified prbs7 and prbs15 gereration code
2016-06-13 14:44:03 -04:00
83dd7e91c4
deleted pn23 and pn 31, data width yet to be modified
2016-06-13 14:44:03 -04:00
341b7badee
library/scripts: Remove all autogenerated interface in adi_ip_properties_lite
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There are a few IP, which is configured by using just the adi_ip_properties_lite
process, therefor the remove_all_bus_interface will be called in the end of that
process, to make sure that all the autogenerated interfaces are deleted during the
IP properties setup.
2016-06-10 15:08:05 +03:00
9d1ae436b1
common/util_pulse_gen: Rename the ad_tdd_sync module
2016-06-09 10:07:47 +03:00
abe837e608
util_rfifo: Set an offset for the write addres
2016-06-02 17:34:29 +03:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
3832f2669e
axi_jesd_xcvr: support tx/rx disable
2016-06-01 13:48:51 -04:00
54f398cc36
ad9371-hw- add dsp slice
2016-06-01 13:48:51 -04:00
e1495b89f9
axi_dacfifo: Cosmetic changes
2016-05-27 14:13:55 +03:00
c724c027c4
axi_dacfifo: Fix the synchronizers
2016-05-27 14:13:55 +03:00
183c67aca0
axi_dacfifo: Update the axi write controller
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Do some refactoring and add a DMA beat counter.
2016-05-27 14:13:55 +03:00
8caa783f5c
axi_dacfifo: Update the constraints
2016-05-27 14:13:55 +03:00
3b6a36e3e2
axi_dacfifo: Increase the ASYM_MEM depth in the DAC side
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Increase the asymetric memory depth on the DAC side. Increase the
data width of the grey coder and decoder.
The controller fills up the CDC memory with three AXI burst, to prevent
underflow on the wrap arounds.
2016-05-27 14:13:55 +03:00
c8d4f956e7
axi_dacfifo: Update the read back logic
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Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
2016-05-27 14:13:55 +03:00
88e0cfec42
axi_dacfifo: The AXI read and write have the same properties
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AXI read and AXI write channel have the same SIZE and LENGTH.
2016-05-27 14:13:55 +03:00
aca3038919
axi_dacfifo: No overflow for DAC
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
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DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
578376c8fe
axi_dacfifo: Add bypass logic
2016-05-27 14:13:55 +03:00
f10c1e6e93
axi_hdmi_tx: Remove hdmi_full_range register
2016-05-27 14:04:40 +03:00
05ac271aff
daq3/a10gx- qsys modifications
2016-05-24 03:15:24 -04:00
d254fa841b
library- altera updates
2016-05-23 10:55:07 -04:00
3f00614bc7
axi_jesd_xcvr: rx/tx only select
2016-05-20 16:13:36 -04:00
f1a603a3b1
ad9371- altera ip
2016-05-20 15:16:36 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
b5b05bb9d1
axi_ad9371: added
2016-05-20 11:41:54 -04:00
bf0b90229a
rfifo/wfifo- qsys ip
2016-05-18 13:24:13 -04:00
7fdaee186c
upack/cpack- qsys ip
2016-05-18 13:24:13 -04:00
a262eb7ab3
ad9361- output-rst - associated-rst issue?
2016-05-18 13:24:13 -04:00
e15893444c
upack- fix interface names
2016-05-18 13:24:13 -04:00
285cbc7225
xfifo- fix sdc/xdc names
2016-05-18 13:24:13 -04:00
d7f0bd1b76
ad9361- add reset sink
2016-05-18 13:24:13 -04:00
bb4ed42a93
ad9361- add missing wires
2016-05-18 13:24:13 -04:00
42b0fabd40
axi_hdmi_tx_core: Fixed data path
2016-05-17 14:41:18 +03:00
68329de738
ad9361- interface updates
2016-05-16 12:19:38 -04:00
421c0519f4
util_rfifo- updates
2016-05-16 12:19:38 -04:00
e05204a86d
util_cpack: interface updates
2016-05-16 12:19:38 -04:00
6bc05fc844
ad_*_in: register post-iob
2016-05-16 12:19:38 -04:00
cd7c9c99ed
ad_*_clk: altera-pll not supported by qsys flow
2016-05-16 12:19:38 -04:00
4fbff45e27
util_wfifo- updates
2016-05-16 12:19:38 -04:00
f515885fc4
util_wfifo: altera ip
2016-05-16 12:19:38 -04:00
58a2a3259c
util_rfifo: updates
2016-05-16 12:19:38 -04:00
82d43783f1
util_rfifo: altera ip
2016-05-16 12:19:38 -04:00
31671bf9d5
util_rfifo: constraints
2016-05-16 12:19:38 -04:00
aadb220a3f
zcu102- updates
2016-05-10 15:40:41 -04:00
3871d3ce2b
ad9361-c5/a10 - updates
2016-05-09 13:54:08 -04:00
9cd6e2da51
quartus-mess- altddio direct instantiation
2016-05-09 13:54:08 -04:00
726ddb6e93
ad_lvds_clk: Fixed assignment mismatched
2016-05-09 10:32:18 +03:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
b36c722ec9
up_hdmi_tx: Discard the standard default values
...
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
2016-05-05 13:41:46 +03:00
68d83def01
axi_hdmi_tx_core: Fixed data path
2016-05-05 13:32:25 +03:00
0d2dc2c62b
axi_hdmi_tx: Fixed data bus width
2016-05-05 13:26:59 +03:00
bdfa383622
library/axi_ad9361: tdd false paths
2016-05-04 13:42:12 -04:00
ef6c99ecab
library/axi_ad9361: hw component updates
2016-05-04 13:42:12 -04:00
3b5e44e37d
library/axi_ad9361: mmcm rst for plls
2016-05-04 13:42:12 -04:00
16a13b2023
library/axi_ad9361: add rst/locked to clock
2016-05-04 13:42:11 -04:00
1aac44b0d9
library: ad_*clk- rst/locked
2016-05-04 13:42:11 -04:00
d82ca5dc3c
library/common- altera variations
2016-05-04 13:42:11 -04:00
b6b68e9ab7
axi_jesd_gt: Split the constraint file
...
-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
2016-05-04 19:32:06 +03:00
583bafd17a
axi_ad7616: Add a new register for IF_TYPE
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Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode.
2016-05-04 16:14:29 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
3f5e1e1203
ad9361- dev_if module name change
2016-04-29 10:17:35 -04:00
89f5d2394e
altera- clock variations
2016-04-29 10:17:35 -04:00
243d3e6e41
ad9361- a10soc sdc files
2016-04-29 10:17:35 -04:00
aa2aa902bf
ad9361- a10soc updates
2016-04-29 10:17:35 -04:00
f411d29e30
ad9361- a10soc changes
2016-04-29 10:17:35 -04:00
3563c2212c
common/altera- removed dcfilt/mul
2016-04-29 10:17:35 -04:00
0260280db1
common/altera- data path
2016-04-29 10:17:35 -04:00
ed62101308
common/altera: primitives
2016-04-29 10:17:35 -04:00
779d014750
ad9361-common alt/xil interface
2016-04-29 10:17:35 -04:00
7ec4c00f9f
axi_ad7616: DMA is always ready
2016-04-29 16:36:33 +03:00
427f85959c
axi_ad7616: Fix the AXI stream interface
2016-04-29 16:34:34 +03:00
33199263e1
axi_ad7616: Delete burst_length register
...
This was an unnecessary feature of the hdl core.
2016-04-29 16:28:48 +03:00
d5d7c12f0e
axi_ad7616: Fix the register map
2016-04-25 11:36:39 +03:00
2ccdd426ec
axi_ad7616: Fix the rd_db_valid generation and do some cosmetic changes.
2016-04-25 11:28:22 +03:00
ad227c1af0
up_axi: Wait more to a valid read acknowledge.
2016-04-25 10:34:17 +03:00
e9b199959a
library/adcfifo- constraints update
2016-04-20 15:57:25 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
d7d8b2cf1c
axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines
2016-04-19 14:38:26 +03:00
e855ef38f4
axi_dacfifo: Initial commit
...
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00
42cd05ab19
ad_mem_asym: Add support for more ratios.
...
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
6fe41ebb08
axi_hdmi_tx: Upgrade hdmi clipping process
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-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
69d721526a
util_dacfifo: Add constraints file
2016-04-12 13:21:50 +03:00
Shrutika Redkar
Istvan Csomortani
Rejeesh Kutty
AndreiGrozav
István Csomortáni
Adrian Costina