Commit Graph

10 Commits (40cbabf57312ab6fddb9173afc427fdacb646d20)

Author SHA1 Message Date
Michael Hennerich a3dbd5ac00 projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-09-16 14:59:36 +02:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Michael Hennerich 647a26e19c projects/common/vc707/vc707_system_bd.tcl: Select Linux MMU settings 2014-09-10 17:40:36 +02:00
Rejeesh Kutty 877b81a373 ad9625/vc707: working version 2014-05-30 15:07:23 -04:00
Istvan Csomortani c5b3dd3643 vc707 base : tcl update
- Added missing address space
    - Connect the sys_audio_clkgen/reset
2014-05-08 12:30:25 +03:00
Istvan Csomortani fbafaa8507 MicroBlaze base system: Fix a few net names
Every interconnect interface net name follows the convention:
	<interconnect name>_<interface name>
	No changes in logic or any connection!
2014-04-01 10:40:35 +03:00
Istvan Csomortani 0f10623be4 AC701/VC707: Define common variables
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
2014-03-25 14:24:51 +02:00
Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
2014-03-24 13:07:48 +02:00
Istvan Csomortani 75963ab376 Initial check in of VC707 base project
- All source files for the VC707 base project
	- Update the common base system to the new naming convention
2014-03-10 17:26:17 +02:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00