Commit Graph

2380 Commits (4050f5ae5808f72e567bd5b6aae2ac1e0af2355c)

Author SHA1 Message Date
Lars-Peter Clausen 5ffd1e1bac common: a10soc: Fix gpio_bd_i constraints
Fix a copy and paste error and specify the IO_STANDARD for all gpio_bd_i
rather than twice for half of them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Istvan Csomortani 2abc7278bf adrv9364z7020: Connect the gps_pps signal to the receiver 2017-07-28 08:08:27 +01:00
Istvan Csomortani be5f2ad80f adrv9361z7035: Connect the gps_pps signal to the receiver 2017-07-28 08:03:33 +01:00
Adrian Costina 5a98e727f2 A10GX: Update DDR3 configuration 2017-07-27 12:38:14 +01:00
Rejeesh Kutty 0aafd049c9 hdlmake.pl- remove ad_lvds 2017-07-26 10:32:44 -04:00
Rejeesh Kutty 893af8d3e6 library & projects- ad_lvds/ad_data replace 2017-07-26 10:31:48 -04:00
Rejeesh Kutty d4820dd55a library- remove ad_cmos_* 2017-07-26 10:20:39 -04:00
Rejeesh Kutty c15db8b74e ad77681evb/zed: ad_lvds-ad_data replace 2017-07-26 10:18:26 -04:00
Rejeesh Kutty 3eeba8273a hdlmake.pl/fmcomms2- updates 2017-07-24 16:33:40 -04:00
AndreiGrozav eb113c8698 fmcomms2_kcu105: Initial commit 2017-07-24 18:45:48 +03:00
Lars-Peter Clausen 374c49ff48 axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains
Qsys allows to query to query the clock domain that is associated with a
clock input of a peripheral. This allows to automatically detect whether
the different clocks of the DMAC are asynchronous and CDC logic needs to be
inserted or not.

Auto-detection has the advantages that the configuration parameters don't
need to be set manually and the optional configuration will be choose
automatically. There is also less chance of error of leaving the settings
in a wrong configuration when e.g. the clock domains change.

In case the auto-detection should ever fail configuration options that
provide a manual overwrite are added as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 16:06:37 +02:00
Rejeesh Kutty 8b31fe73e0 hdlmake.pl updates 2017-07-21 10:37:56 -04:00
Nick Pillitteri 2d64d43475 ZCU102: SPI assign chip selects individually
Otherwise, Vivado 2016.4 sets all of the CSNs equal to CSN0. This fix is needed to get the FMCOMMS5 working properly on the ZCU102 (#36)
2017-07-21 09:22:10 +01:00
Rejeesh Kutty a8ade15173 hdlmake.pl - updates 2017-07-20 15:11:21 -04:00
Rejeesh Kutty d132ed45cd arradio- timing violations fix 2017-07-20 15:08:21 -04:00
Lars-Peter Clausen 669a2da735 common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the
same clock domain. They are both driven by the same clock. And even though
qsys is capable of detecting this it seems qsys interconnect is not able to
infer this and inserts a extra clock domain crossing bridge between the DMA
and the HPS AXI system memory interface.

To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so
that all components are driven by the same qsys clock signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:27 +02:00
Rejeesh Kutty 3ef00475bc arradio/c5soc- clocking changes 2017-07-20 13:05:07 -04:00
Rejeesh Kutty f3ad2e24c1 rfsom2/ccbox- rtc int 2017-07-20 09:25:09 -04:00
Rejeesh Kutty 8c60a2a850 rfsom/ccbox- rtc int 2017-07-20 09:22:45 -04:00
Rejeesh Kutty c11d7d9fda rfsom2/ccbox- tsw s5 fix 2017-07-19 14:23:54 -04:00
Rejeesh Kutty d969b9ea9f rfsom2/ccbox- tsw updates 2017-07-18 13:53:44 -04:00
Rejeesh Kutty becc3e8628 rfsom/ccbox- tsw updates 2017-07-18 13:51:37 -04:00
Lars-Peter Clausen 2e173201d4 daq2: daq2_qsys.tcl: Use sys_dma_clk
Use the sys_dma_clk clock module for clock and reset signals of the data
path, rather than using the A10GX specific sys_ddr3_cntrl signals. This
enables compatibility for all Altera/Intel platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:38:20 +02:00
Adrian Costina 711cb66985 adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary 2017-07-14 10:20:57 +03:00
Istvan Csomortani 98cf18dd51 daq3/zc706: Fix system_top instantiation
Delete used interrupt ports: the ps_intr_10 and ps_intr_11 is used by
the jesd cores.
2017-07-06 13:29:09 +01:00
Istvan Csomortani b4a25223fa plddr3_dacfifo_bd: Increase the AXI burst length to max
Increase AXI burst length to maximum value, to support higher
data rates.
2017-07-06 10:15:06 +01:00
Lars-Peter Clausen debca3a153 fmcjesdadc1: vc707: Remove unsed mb_intrs signal
The mb_intrs signal is never driven, it is a leftover of an earlier version
of the file, remove it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:38:25 +02:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Lars-Peter Clausen b0ebf2df06 daq3: Provide DAC JESD204 lane mapping
The DAQ3 does not use a 1-to-1 lane mapping for the DAC JESD204 link.
Provide the proper mapping when setting up the transceiver connections.
Without this the payload data will be mapped incorrectly and the
transmitted signals are scrambled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-30 16:01:10 +02:00
Adrian Costina d65a543854 kc705: Fix ethernet address span 2017-06-30 14:23:01 +03:00
AndreiGrozav a765a9c709 arradio: Add i2c interface 2017-06-29 17:26:58 +03:00
Istvan Csomortani 6ebef5dde0 make: Update make files 2017-06-26 15:51:19 +01:00
Istvan Csomortani ca12938873 ad77681evb: Suppress a critical warning 2017-06-22 14:25:43 +01:00
Istvan Csomortani 1541943ff2 adrv9371_alt: Delete the fifos from the RX path
+ Delete the rx_fifo and rx_os_fifo from the RX datapath
  + Change the receive DMA's source interface type to wr_fifo
2017-06-22 11:58:10 +01:00
Lars-Peter Clausen 2e8be3d7a6 daq2: Provide DAC lane map
Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 4bf5990451 adi_board.tcl: ad_xcvrcon: Add lane mapping support
Add a parameter to the ad_xcvrcon function that allows to provide a mapping
between logical and physical lanes. By default if no lane map is provided
the logial and physical lanes are mapped 1-to-1. If a lane map is provided
logical lane $n is mapped onto physical lane $lane_map[$n].

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Rejeesh Kutty 56867b362e daq3- updated to 12.5G 2017-06-16 09:02:26 -04:00
Rejeesh Kutty 3fb5408acc fmcjesdadc1/a10gx- fix sysref, lvds io and such 2017-06-15 13:57:21 -04:00
Rejeesh Kutty 6ec9eab7b9 fmcjesdadc1/a10soc- fix sysref, lvds io and such 2017-06-15 13:57:21 -04:00
Rejeesh Kutty ef290ef484 hdlmake.pl updates 2017-06-15 11:42:44 -04:00
Rejeesh Kutty e33e6a84f4 a5gt/a5soc - removed 2017-06-15 11:41:28 -04:00
Rejeesh Kutty a23fb793a0 a5gt/a5soc - removed 2017-06-15 11:40:58 -04:00
Rejeesh Kutty 2649458b6d hdlmake.pl updates 2017-06-15 10:21:57 -04:00
Rejeesh Kutty fd0c7f1b1c usdrx1/a10gx- updated to a10gx 2017-06-15 10:21:57 -04:00
Rejeesh Kutty 0311ed411c usdrx1/a10gx- added 2017-06-15 10:21:57 -04:00
Rejeesh Kutty 7ac083b932 fmcjesdadc1/a10soc- sysref fixes 2017-06-15 10:15:59 -04:00
Rejeesh Kutty 004aee930b fmcjesdadc1/a10gx- fix sysref, gpio connections 2017-06-14 14:40:23 -04:00
Rejeesh Kutty dba419239b hdlmake.pl updates 2017-06-14 10:41:14 -04:00
Rejeesh Kutty 3299d244fe fmcjesdadc1: a10gx/a10soc 2017-06-14 10:39:57 -04:00
Rejeesh Kutty 38c708d4d0 fmcjesdadc1: a10gx/a10soc 2017-06-14 10:39:38 -04:00
Rejeesh Kutty 051c1d6644 fmcjesdadc1: a10soc 2017-06-13 15:00:22 -04:00
Rejeesh Kutty c1bc1259a7 fmcjesdadc1: a10gx 2017-06-13 12:39:45 -04:00
Rejeesh Kutty 3f3ea5f99a hdlmake.pl- updates 2017-06-13 09:55:08 -04:00
Rejeesh Kutty ffb6cd4b0b scripts- add a5soc device 2017-06-13 09:54:01 -04:00
Rejeesh Kutty ff646b0cfc common/a5soc- alt 16.1 updates 2017-06-13 09:54:01 -04:00
Rejeesh Kutty 0eacde9158 fmcjesdadc1/a5soc- alt 16.1 updates 2017-06-13 09:54:01 -04:00
Rejeesh Kutty 6decba3c3b hdlmake.pl updates 2017-06-09 16:23:17 -04:00
Rejeesh Kutty 74f9a99655 fmcjesdadc1/a5gt- altera 16.1 updates 2017-06-09 16:20:49 -04:00
Rejeesh Kutty 2e17e67627 common/a5gt- altera 16.1 updates 2017-06-09 16:20:15 -04:00
Rejeesh Kutty 688758e6c6 scripts/adi_project_alt- add a5soc, a5gt 2017-06-09 16:19:29 -04:00
Rejeesh Kutty ca536d50ac altera 16.1 c5soc updates 2017-06-08 15:03:03 -04:00
Rejeesh Kutty f3af192f30 altera 16.1 arradio updates 2017-06-08 15:02:46 -04:00
Rejeesh Kutty ca20309166 adi_project_alt: add c5soc 2017-06-08 15:02:24 -04:00
Rejeesh Kutty b8a75a7285 hdlmake.pl - updates 2017-06-07 10:23:20 -04:00
Rejeesh Kutty 6100a697e8 daq3/a10gx- alt 16.1 updates 2017-06-07 10:23:20 -04:00
Rejeesh Kutty 40bfd0380e adrv9371x/a10gx- alt 16.1 updates 2017-06-07 09:19:14 -04:00
Istvan Csomortani 83747ddb33 ad77681evb: Fix IO constraints 2017-06-07 14:28:39 +03:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Rejeesh Kutty d1bab7ddb9 hdlmake.pl- updates 2017-06-06 16:10:05 -04:00
Rejeesh Kutty 3f92381bd0 daq2/a10gx- project/constraint updates 2017-06-06 16:09:15 -04:00
Rejeesh Kutty dd48929327 hdlmake.pl - updates 2017-06-06 12:25:35 -04:00
Rejeesh Kutty 5176e427a1 common/a10soc- add project create tcl procedure 2017-06-06 12:24:13 -04:00
Rejeesh Kutty f278b6e6c9 adrv9371x/a10soc- constraints/project updates 2017-06-06 12:23:26 -04:00
Rejeesh Kutty e34057c2b2 adrv9371x/a10gx- constraints/project updates 2017-06-06 12:22:31 -04:00
Rejeesh Kutty e9c49f667f altera- 16.1.2 & a10soc 2017-06-06 12:20:44 -04:00
Adrian Costina 578ccaaa44 adrv9371x:a10gx, update create project command and Makefile 2017-06-06 17:30:12 +03:00
Adrian Costina 54a53c015a scripts: changed adi_project_create command to adi_project_altera 2017-06-06 17:29:12 +03:00
Adrian Costina 0d99aa02e1 m2k: Updated project to work with the fifo_depth related changes 2017-06-06 15:37:23 +03:00
Istvan Csomortani 491602d88b make: Update make files 2017-06-06 12:00:40 +03:00
Rejeesh Kutty 6df97a61ae adrv9364z7020- fix enable/en_agc mixup 2017-06-05 16:06:27 -04:00
Rejeesh Kutty eadbf9ae30 altera- remove default assignments from procedure 2017-06-05 15:25:38 -04:00
Rejeesh Kutty 0bd22e78d9 altera- adi-project-create version 2017-06-05 15:24:35 -04:00
Rejeesh Kutty 1b1c7ffa61 adi_project- altera version 2017-06-05 15:13:21 -04:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Rejeesh Kutty 2d56141bbd altera- 2017-r1 16.1.2 2017-05-30 12:21:27 -04:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 669e0a01d0 fmcomms2/a10gx: Remove project 2017-05-26 17:05:55 +03:00
Istvan Csomortani 3c47d00a96 daq1/a10gx: Remove project 2017-05-26 17:05:28 +03:00
Istvan Csomortani 414943db4b m2k: Fix Make files 2017-05-26 09:54:08 +03:00
Istvan Csomortani c4fa41e4e5 adrv9364z7020: Update README 2017-05-25 17:47:58 +03:00
Istvan Csomortani 3af00dc520 adrv9361z7035: Update README 2017-05-25 17:47:19 +03:00
Istvan Csomortani 9ecfcce4ec adrv9364z7020: Rename pzsdr1 to adrv9364z7020 2017-05-25 17:20:23 +03:00
Istvan Csomortani 26822af7e1 adrv9361z7035: Rename pzsdr2 to adrv9361z7035 2017-05-25 17:17:54 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Adrian Costina f9057b1825 m2k: Add scale correction option. Update parameters 2017-05-24 15:59:24 +03:00
Lars-Peter Clausen 4d00439d52 fmcomms11: Convert to ADI JESD204
Convert the FMCOMMS11 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen d4c9f1e9f1 fmcjesdac1: Convert to ADI JESD204
Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The
change is very straight forward, but a matching change on the software side
is required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 9a917ae8bf fmcadc4: Convert to ADI JESD204
Convert the FMCADC4 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen bbe457acea fmcadc2: Convert to ADI JESD204
Convert the FMCADC2 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00