Commit Graph

8 Commits (3e3955ce91f975bfd8ac86bb56e0112c9e47516d)

Author SHA1 Message Date
AndreiGrozav a23c640180 Require Vivado 2017.2.1 for all zcu102 projects 2017-11-20 15:36:51 +00:00
AndreiGrozav f1e51a8b89 adrv9371x_zcu102: Fix rx_div_clk constraint placement 2017-11-20 15:36:51 +00:00
Lars-Peter Clausen 46acdadb92 adrv9371x: Set correct transceiver type for UltraScale projects
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.

This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.

It is also necessary for correct eye scan support in the axi_adxcvr block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
Lars-Peter Clausen caac2ce588 adrv9371x: zcu102: Fix lane mapping
Fix the location assignment of the transceiver blocks to get the correct
lane mapping.

Note that the comments indicating the expected lane mapping are correct,
but the actual transceiver location assignments were not.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
Lars-Peter Clausen f181e037cc adrv9371x: zcu102: Fix QPLL feedback divider
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
AndreiGrozav 22808fa03c zcu102: Update to rev 1.0 2017-11-08 10:33:12 +02:00
Istvan Csomortani 700ed156ab [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx 2017-09-25 08:56:40 +01:00
AndreiGrozav d05ed29212 adrv9371x_zcu102: Initial commit 2017-08-22 15:48:03 +03:00