Commit Graph

6261 Commits (3e297f54dde3c58d39db50a4716c10ace588329e)

Author SHA1 Message Date
Istvan Csomortani 65af205d6b axi_dmac: Add axis_last control signal to the Master AXI Streaming interface
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
2015-05-06 13:54:31 +03:00
Adrian Costina 4f75414a1a fmcomms1: Removed constraints that are not needed 2015-05-05 23:39:08 +03:00
Adrian Costina 1fcaf8fb63 fmcomms1: Updated AC701 project to meet timing. Reduced FIFO size for AD9643 DMA to 8 2015-05-05 23:37:01 +03:00
Adrian Costina 90a5bb81b6 cftl_cip: Updated project to work with the new util_pmod_adc core 2015-05-05 23:34:52 +03:00
Adrian Costina 233cc111d2 util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz 2015-05-05 23:33:13 +03:00
Adrian Costina 95805f21fa adv7511: Fixed system_top for mitx045 board 2015-05-05 10:08:11 +03:00
Adrian Costina 3517b6941c adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale 2015-05-05 10:06:26 +03:00
Rejeesh Kutty 319f821fab zc706pr - makefile 2015-05-04 13:41:03 -04:00
Rejeesh Kutty ab85e2ba36 zc706pr - 706 partial reconfiguration 2015-05-04 12:36:57 -04:00
Rejeesh Kutty e489090fbb scripts- initialize prcfg list 2015-05-04 12:34:19 -04:00
Rejeesh Kutty 2a8703763e zc706pr - 706 partial reconfiguration 2015-05-04 12:33:28 -04:00
Rejeesh Kutty c3dd9258e7 zc706: project mode 2015-05-04 10:25:12 -04:00
Rejeesh Kutty 62acd37fee zc706: project mode 2015-05-04 10:25:07 -04:00
Rejeesh Kutty 707b285669 prcfg: bb def 2015-05-04 10:24:13 -04:00
Istvan Csomortani e7a0da9089 fmcomms2 : Verify the existence of the PR license
The fmcomms2 runs by default on PR mode, if the project script does not find a PR license, will implement just the default mode.
2015-05-04 15:12:38 +03:00
Rejeesh Kutty 4bb26caa13 itx045: default install 2015-05-01 16:19:10 -04:00
Rejeesh Kutty ad551a0073 itx045: updates 2015-05-01 16:18:43 -04:00
Rejeesh Kutty aced144916 itx045: updates 2015-05-01 16:18:23 -04:00
Rejeesh Kutty ff443655ca itx045: add ps7 settings 2015-05-01 16:17:59 -04:00
Rejeesh Kutty 26fb85583b adi_project- prefix directory for gitignore & make clean 2015-05-01 13:18:12 -04:00
Rejeesh Kutty ff985875a0 gitignore: add non-project stuff 2015-05-01 13:17:14 -04:00
Rejeesh Kutty 00cafd4df0 fmcomms2/zc706: add partial reconfiguration 2015-05-01 12:23:18 -04:00
Rejeesh Kutty 3641d8f714 fmcomms2/zc706: add partial reconfiguration 2015-05-01 12:23:11 -04:00
Rejeesh Kutty 75a81d67d8 fmcomms2/zc706: add partial reconfiguration 2015-05-01 12:23:07 -04:00
Rejeesh Kutty 0dc4c9cda9 adi_project: added partial reconfiguration 2015-05-01 12:21:59 -04:00
Rejeesh Kutty 140c622c8b prcfg: common files 2015-05-01 11:48:09 -04:00
Rejeesh Kutty a8d4c916c1 fmcomms2_bd: remove axi3 switch 2015-05-01 11:47:29 -04:00
Adrian Costina be32715ab3 axi_adcfifo: Updated constraints 2015-04-30 14:23:24 +03:00
Adrian Costina 3b58785368 daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints 2015-04-30 12:14:03 +03:00
Adrian Costina e332fa01c8 ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection 2015-04-30 12:11:46 +03:00
Adrian Costina d623f77453 axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
Adrian Costina 463c4d4d28 util_wfifo: Added constraint for the resetn path 2015-04-30 12:05:02 +03:00
Adrian Costina 392ba31a07 axi_hdmi_rx: Updated constraints 2015-04-30 12:04:15 +03:00
dbogdan 1df48a2e6e Add hdmiio_int pin. 2015-04-29 18:50:28 +03:00
Adrian Costina 19ef85cec3 vc707: Changed mig project to use BANK_ROW_COLUMN, as it seems this mode gives best performance 2015-04-28 17:15:58 +03:00
Adrian Costina 288b9cccff Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file 2015-04-28 15:22:37 +03:00
Adrian Costina 252aa135eb ad9739a: Changed dma and interconnect clock to 200mhz. Removed div_clk constraint, as it is autodetected 2015-04-28 15:14:31 +03:00
Adrian Costina a7a2d194e9 axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core 2015-04-28 15:04:18 +03:00
Adrian Costina 3fdda617a4 fmcomms1: updated common, changed DMAC fifo size and wfifo reset signal source
- changed DMAC FIFO size to 16, as it should be large enough
- connected wfifo reset to adc_rst from axi_ad9643 core
2015-04-28 14:58:04 +03:00
Adrian Costina 37bfb2ef4b ad9265: Updated common, wfifo is reset by the adc_rst signal from axi_ad9265 core 2015-04-28 14:53:12 +03:00
Adrian Costina c36186f75a axi_ad9643: Added adc_rst output 2015-04-28 14:52:24 +03:00
Adrian Costina 8ee3f64a65 axi_ad9265: Added adc_rst output 2015-04-28 14:51:14 +03:00
Adrian Costina 67c581cef8 util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain 2015-04-28 14:50:00 +03:00
dbogdan 1eebfd3155 projects/imageon_loopback: Initial commit. 2015-04-28 10:32:28 +03:00
Adrian Costina e51edfbadb adv7511: KC705 mdio pin name fix 2015-04-27 11:21:36 +03:00
Adrian Costina 7e6f2bfa15 ad9265: Updated constraints file. 2015-04-27 11:20:42 +03:00
Adrian Costina 1ad87aa27c util_wfifo: Added constraints 2015-04-27 11:19:56 +03:00
Adrian Costina 81d4e1d9b1 axi_clkgen: Updated constraints 2015-04-27 11:19:15 +03:00
Adrian Costina d950f5ffcd axi_ad9122: Updated constraints 2015-04-27 11:18:52 +03:00
Istvan Csomortani 9fba4cb2ef util_dacfifo: Add support for Slave AXI stream interface.
The FIFO can be initialized through an AXI stream interface too.
2015-04-27 10:40:55 +03:00