07316a905e
daq3/a10gx: sysref is lvds
2015-12-14 09:29:10 -05:00
ee4d5af12e
ad7616_sdz: Update the project
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+ Fix system_top.v
+ Finish up the common block design
+ Fix system_project.tcl
2015-12-14 16:02:38 +02:00
8ae9de8fba
axi_ad7616: Update core
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+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
4e57170384
spi_engine: Update SPI Engine frame work
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+ data width and number of SDI lines are configurable
+ axi_spi_engine module can have two different type of memory map interface (S_AXI or UP)
2015-12-14 15:57:54 +02:00
29a0f27cd1
ad_edge_detect: Add a flop to output, reset is active high
2015-12-14 15:40:29 +02:00
f4e3523390
ad7616_sdz: Update IO constraints
2015-12-14 15:34:56 +02:00
6a9d1c431a
daq3/a10gx: updated to a10gx/quartus
2015-12-11 12:49:25 -05:00
4c2d08a9be
ad9152: altera syntax error
2015-12-11 12:49:00 -05:00
da2e1bdc9a
daq2/a10gx: 32bits generic gpio
2015-12-11 11:50:26 -05:00
650d426301
a10gx/base: set gpio to 32
2015-12-11 10:14:37 -05:00
dc84a9ad82
daq3/a10gx: updates
2015-12-10 16:06:14 -05:00
f1b6577447
a10gx/base: separate gpio in/out
2015-12-10 16:04:54 -05:00
bc93910ee5
ad9152: qsys updates
2015-12-10 16:04:10 -05:00
ff1d98a0c7
ad9144: duplicate include
2015-12-10 16:02:35 -05:00
ce906989d5
ad9152: qsys ip
2015-12-10 09:46:31 -05:00
d944198212
daq3/a10gx: board updates
2015-12-10 09:45:20 -05:00
1a38ea205d
daq3/a10gx: copy
2015-12-10 09:42:56 -05:00
614babc18e
daq3/kcu105: copy
2015-12-10 09:41:47 -05:00
b0fef1122e
daq3/a10gx: copy
2015-12-10 09:41:37 -05:00
be075379df
hdlmake: updates
2015-12-07 13:11:24 -05:00
0938041d97
ad7768evb: added
2015-12-07 13:07:03 -05:00
12c95b059d
ad_tdd_control: Remove tdd_enable_synced control line
...
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
5cf45b2978
axi_clkgen: Added phase related parameters
2015-12-02 18:50:23 +02:00
6e549171f0
fmcomms5: Connected the clk input of the ad9361 to l_clk
2015-12-02 14:43:44 +02:00
2309c4d83c
Makefiles: Removed " from path
2015-11-27 14:02:46 +02:00
159f6c1216
Makefiles: Updated Makefiles
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- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
36febf8591
Merge branch 'master' into dev
...
Conflicts:
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_dmac/Makefile
library/axi_dmac/axi_dmac_constr.ttcl
library/axi_dmac/axi_dmac_ip.tcl
library/common/ad_tdd_control.v
projects/daq2/common/daq2_bd.tcl
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms2/zc706pr/system_project.tcl
projects/fmcomms2/zc706pr/system_top.v
projects/usdrx1/common/usdrx1_bd.tcl
This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
667e49fe41
library: Axi_clkgen, added register for controlling the source clock.
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Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
ea57b3c03c
daq2: A10GX, add project specific IP search paths
2015-11-25 10:58:36 +02:00
df58646925
util_adcfifo: Updated altera interface
2015-11-25 10:20:06 +02:00
e8a595b81e
fmcjesdadc1: Updated a5soc design
2015-11-24 15:39:52 +02:00
fd3910a915
fmcjesdadc1: Updated a5gt design
2015-11-24 15:39:21 +02:00
9281eb2c33
fmcjesdadc1: Updated common altera design
2015-11-24 15:38:58 +02:00
593c486168
ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received
2015-11-24 15:15:53 +02:00
c70be7391f
ad_tdd_control: Avoid unnecessary reset on control lines
...
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
a81625e1fa
daq2: Updated a10gx project
2015-11-24 13:28:53 +02:00
605a0768e0
arradio: Updated c5soc project
2015-11-24 13:27:44 +02:00
a0e67aad56
c5soc: Updated common design
2015-11-24 13:22:01 +02:00
ee0617661e
axi_ad9680: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:45:12 +02:00
f51871c1e4
axi_ad9144: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:44:07 +02:00
76823f95fa
axi_ad9250: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:39:55 +02:00
275ec3d3a8
axi_ad9361: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:21:08 +02:00
250f3c917b
axi_ad9361: Removed old signals from the altera device interface module
2015-11-24 11:20:35 +02:00
fb269f7a29
util_cpack: Updated altera interfaces
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- DMA side, simplified naming
- ADC side, added FIFO conduit per channel
2015-11-24 11:18:18 +02:00
e6de2ade78
util_upack: Updated altera interfaces
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- DMA side, simplified naming
- DAC side, added FIFO conduit per channel
2015-11-24 11:17:02 +02:00
c5ff1674c6
axi_dmac: Updated fifo interfaces for easier connectivity
2015-11-24 11:08:28 +02:00
e5d2f5be06
util_upack: Cosmetic changes
2015-11-24 10:55:10 +02:00
985f2ca020
library: ad_rst, added comment so that the registers are not minimized away
2015-11-24 10:33:38 +02:00
c051a578e5
fmcomms2: Delete unnecessary clock definition
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The two clocks, rx_clk and ad9361_clk, are the same.
2015-11-20 19:35:37 +02:00
c15c82d9d1
ccpci- remove ps7 ddr hp0 access
2015-11-19 16:42:02 -05:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina