Commit Graph

3337 Commits (3e297f54dde3c58d39db50a4716c10ace588329e)

Author SHA1 Message Date
LIacob106 3e297f54dd projects/adrv9009zu11eg: expose jesd params to make and add FMCOMMS8 parameter
Expose JESD parameters to make.
Add FMCOMMS8 parameter.
Changed the name of the observation path to match the rest of the repo.
Replace old dac_data_width formula with a more generic one.
2022-09-26 14:26:31 +03:00
PopPaul2021 8a77d4fb05
coraz7s: Memory interconnect fix (#1014) 2022-09-23 14:58:43 +03:00
Iulia Moldovan 474b8d5bed cn0577/zed: Update xdc to diff_term true. Disable csn in system_top
* Update xdc to use diff_term true instead of diff_term 1
 * Generated xdc using adi_fmc_constr_generator.tcl
 * Make CSN to be inactive
 * Cosmetic changes also

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-09-21 09:42:40 +03:00
laurent-19 6b94259a52 projects/common: Add system_top _project templates
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct code and modify according to guidelines

* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct/Add missing wrapper ports and iobufs

* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

ac701/system_top.v: Change top based on previous projects

 * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

projects/common: Modify templates to build without errors

* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
	 system_project: Added adi_board, adiobuf sourcing
	 system_top: Removed hdmi, i2c, fanpwm, spdif ports
		     according to base design
* c5soc: Added version settings
	 Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
	    system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
	 Removed unnecessary ports

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Delete microzed vmk_es templates

* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-20 17:00:49 +03:00
AndrDragomir 7cde7cd048 projects/scripts: Add fmc constraints generator script
Using the script:
  - make sure that the eval board in use has a common fmc connection file.
  if you created a new one, it should be saved as &project_name_fmc.txt inside
  &project_name/common
  - open a tcl terminal, either inside or outside the project
  - make sure your current directory is &hdl_repo/projects/&project_name/&carrier
  - source the script found at &hdl_repo/project/scripts/fmc_constr_generator.tcl
  - call gen_fmc_constr $parameter_1 $parameter_2:
      - in case of only one fmc port on the carrier call without any parameters
      - if there are two fmc ports on the carrier and you want to use only one,
      the first parameter should contain an indication (fmc_lpc/hpc, fmc0/1, etc.)
      - if there are two fmc ports on the carrier and you want to use both, then
      both parameters should contain an indication
  - the constraints file will be generated in the current directory

Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2022-09-20 14:11:08 +03:00
AndrDragomir 72378a6d4a projects: Add fmc connection files for eval boards
Creating a new eval board fmc file:
  - docs: Open FMC_eval_board_template.xlsx
  - follow the instructions on the first sheet
2022-09-20 14:11:08 +03:00
AndrDragomir 72cf8f9b5d projects/common: Add fmc connection files for every platform 2022-09-20 14:11:08 +03:00
LIacob106 158c10df34 projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
Laszlo Nagy d20e604864 ad9082_fmca_ebz/zcu102: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Laszlo Nagy e332409610 ad9081_fmca_ebz: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Ionut Podgoreanu 5a06f186ae ad9081_fmca_ebz/common: Use the script to compute the TPL width 2022-08-25 12:35:42 +03:00
AndreiGrozav f955fbc6c0 adi_pd.tcl: Fix sysid branch string
For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
  dev_new_device^[[m"

The above escape codes will mess up a terminals color scheme  when this
information is read from sysid and displayed on a terminal.

Use --no-color flag to fix this issue.
2022-08-25 11:36:25 +03:00
Iulia Moldovan 388611866a projects: Fix some Makefiles
* ad9082_fmca_ebz/vcu118
 * dac_fmc_ebz/vcu118

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-25 09:35:55 +03:00
ladace cf4e1b79cf
scripts:adi_env: Change the default version of Quartus Standard to 21.1 (#996)
New version of Quartus Standard for de10nano and sockit  was changed
to 21.1.

Signed-off-by: Liviu Adace <liviu.adace@analog.com>

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-08-24 17:01:06 +03:00
PopPaul2021 cc18f90579
Added axi_ad7768 IP Core (#989)
* projects/ad7768evb: Initial commit with axi_ad7768 IP

* library/axi_ad7768: Initial commit for AD7768/AD7768-4
2022-08-24 16:57:14 +03:00
ladace 4307e3071f
scripts:adi_env: Change the default version of Quartus Pro to 21.4 (#988)
New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
2022-08-18 17:08:29 +03:00
Iulia Moldovan dde37124a4 scripts: Update Vivado version to 2021.2
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
PopPaul2021 0595f93452
AD777x support for ZedBoard and DE10Nano (#937)
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.

* library/axi_ad777x: Initial commit for Xilinx and Intel

* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
2022-08-10 11:29:05 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Laszlo Nagy d48b1bcdce ad9081_fmca_ebz/vck190: Expose ref clock parameter 2022-08-04 09:52:57 +03:00
Laszlo Nagy 78333b2c90 ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx 2022-08-04 09:52:57 +03:00
Laszlo Nagy 3379dd3bdb ad9082_fmca_ebz/zcu102: Make JESD_MODE overwritable 2022-08-04 09:50:18 +03:00
Liviu.Iacob 54a22d036c adi_pd.tcl: Fix git_clean_string logic 2022-08-02 17:11:49 +03:00
Sergiu Arpadi 94c4a291a7 cn0561_coraz7s: Fix gpio connections 2022-08-02 17:11:19 +03:00
Sergiu Arpadi bb3027995a sysid: Add sysid support for de10nano
make adv7513

make 0540
2022-08-02 14:15:34 +03:00
Laszlo Nagy c748b3bbc7 ad9082_fmca_ebz/zc706: Fix parameters
Match default parameters for L=4 M=8 mode with 10Gbps.
The L=8 M=4 would require lane rate of 15Gbps that is not supported on
zc706.
2022-08-01 16:40:03 +03:00
Laszlo Nagy aae7971689 ad9082_fmca_ebz/vcu118: Fix default lane rate parameter 2022-08-01 16:40:03 +03:00
Laszlo Nagy aed7032e0c ad9082_fmca_ebz/zcu102: Fix default lane rate parameter 2022-08-01 16:40:03 +03:00
Laszlo Nagy 2b274f945f ad9081_fmca_ebz: Reset cpack with Rx data offload 2022-08-01 12:47:26 +03:00
Filip Gherman d48ab915a5 vcu128: Connect sys_mb_rstgen/ext_reset_in accordingly
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-07-29 20:05:08 +03:00
alin724 6aa899f161 scripts/adi_project_xilinx.tcl: Add new constraints file support 2022-07-20 14:36:04 +03:00
alin724 9864d96096 Merge CN0506 projects into a parameterized one 2022-07-20 14:36:04 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Laszlo Nagy 171daab8f2 ad9081_fmca_ebz: a10soc: Update resistor change comment
A board rework is required so the clocks, chip selects or sync signal reach the part correctly.  Without this the link will not come up.
2022-06-21 14:19:58 +03:00
Laszlo Nagy a8174ac038 ad_quadmxfe1_ebz/vcu118/system_project.tcl: Update comments
Update PLL selection docs.
2022-06-08 15:35:47 +03:00
ladace 6525a37375
ad_fmclidar1_ebz:a10soc Fixed problems with SPI communication with AD9094 (#951)
Now CPH and CPOL are set to 1, also the SPI clock is set to 10MHz

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-06-06 13:00:45 +03:00
PopPaul2021 4f4825a3df
projects:daq2:common: fix adi_tpl_jesd204_rx_create error. (#952)
(\ character has to be removed or a blank line inserted before ad_ip_parameter)
Fix for : 0b8585a6f commit.
2022-06-06 08:53:07 +03:00
PopPaul2021 0b8585a6f1
PN mismatch DAQ2, DAQ3 and FMCJESDADC1 fix (#950)
The AD9680 is a dual 14-bit ADC.
Software sets the output format to offset binary before performing the PN tests.
2022-06-02 14:09:36 +03:00
Ionut Podgoreanu f957d81db1 ad9083_evb_bd: Connect util_ad9083_rx_cpack reset to adc_rst 2022-05-27 09:20:09 +03:00
Filip Gherman 1ae375f4fb ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-05-27 00:48:34 +03:00
Filip Gherman 5ad9dfd6c0 vcu118: Increase Microblaze performance and clock frequency
Increased the Microblaze performance for the VCU118 carrier:
- Increased the size of Instruction Cache and Data Cache to 64kB

Increased the Microblaze clock frequency:
- Using the DDR4 Controller to generate a new sys_mb_clk of 214 MHz to drive all the Microblaze interfaces at higher frequencies

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-05-27 00:48:17 +03:00
Laszlo Nagy bdd5686e95 ad9081_fmca_ebz/a10soc: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy a2da965391 ad9081_fmca_ebz/vck190: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy 20b89ddd99 ad9081_fmca_ebz/vcu128: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy b3d231e569 ad9081_fmca_ebz/zc706: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
ladace ab5c344c89
ad_fmclidar1_ebz:a10soc Fixed SPI communication on Arria 10 (#947)
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-05-24 12:44:03 +03:00
Adrian Costina 08a5e944f0 cn0577: Initial commit
Created a virtual clock to constrain cnv_en.
Given that the cnv_en should be asserted only once per 8 clock
cycles and only the rise edge is of interest, we can constrain
the path as multicycle path.
2022-05-18 18:23:38 +03:00
Adrian Costina 0c3ec108aa ad9213_dual_ebz: Add possibility to change order of channels through a GPIO 2022-05-17 15:27:39 +03:00
Adrian Costina 496b4ec748 ad9213_dual_ebz: Fix constraints
- added sysref constraint
- remove false path from the GPIO pins
2022-05-17 15:27:39 +03:00
AndreiGrozav ef377e58be ad9083_evb_bd: make the project more generic
Allow external parameters and a more flexible configuration.
2022-05-12 16:11:17 +03:00