Commit Graph

4 Commits (3d407a3ba5ea56ef0f9c69c27b68ea9f77a5048f)

Author SHA1 Message Date
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Istvan Csomortani 1b42312157 jesd204:rx_ctrl: Fix the cfg_links_disable mask 2018-05-03 18:48:54 +03:00
Istvan Csomortani 0e099b6f08 jesd204_rx: Add dynamic multi-link support
A multi-link is a link where multiple converter devices are connected to a
single logic device (FPGA). All links involved in a multi-link are synchronous
and established at the same time. For a RX link this means that the SYNC signal
needs to be propagated from the FPGA to each converter.

Dynamic multi-link support must allow to select to which converter devices on
the multi-link the SYNC signal is propagated too. This is useful when depending
on the usecase profile some converter devices are supposed to be disabled.

Add the cfg_links_disable[0x081] register for multi-link control and
propagate its value to the RX FSM.
2018-05-03 18:48:54 +03:00
Istvan Csomortani 09ff1f3a77 jesd204: Fix file names
All the file names must have the same name as its module. Change all the
files, which did not respect this rule.
Update all the make files and Tcl scripts.
2018-04-11 15:09:54 +03:00