Commit Graph

10 Commits (3d407a3ba5ea56ef0f9c69c27b68ea9f77a5048f)

Author SHA1 Message Date
Laszlo Nagy 87b67ced17 jesd204_rx: Interrupt for unexpected lane status error 2020-07-31 11:43:41 +03:00
Laszlo Nagy 5e16eb85bb jesd204_rx: Generate interrupt on frame alignment error
When frame alignment error monitoring is enabled and error threshold is met
at least for one lane, generate an interrupt so software can reset the link and
do further bring-up steps.
2020-07-31 11:43:41 +03:00
Laszlo Nagy 15e14c76b9 jesd204_rx: Don't auto reset on frame alignment error by default
Let software handle the error case by default. Other steps might be
required to bring-up properly the link if one shot SYSREF is used.
2020-07-31 11:43:41 +03:00
Matt Blanton 1e04b2e2f2 jesd204_rx: Add RX frame alignment character check
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
2020-07-31 11:43:41 +03:00
Laszlo Nagy d1072847df jesd204_rx: 64b mode support for receive peripheral
Instantiate 64B/66B decoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
Laszlo Nagy b90c2e79dc jesd204_rx: add parameter for input pipeline stages
Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
2019-05-16 13:29:34 +03:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Adrian Costina 3b9f733408
jesd204: Add RX error statistics (#98)
* jesd204: Add RX error statistics

Added 32 bit error counter per lane, register 0x308 + lane*0x20

On the control part added register 0x244 for performing counter reset and counter mask
Bit 0 resets the counter when set to 1
Bit 8 masks the disparity errors, when set to 1
Bit 9 masks the not in table errors when set to 1
Bit 10 masks the unexpected k errors, when set to 1

Unexpected K errors are counted when a character other than k28 is detected. The counter doesn't add errors when in CGS phase

Incremented version number
2018-05-07 15:33:00 +03:00
Istvan Csomortani 0e099b6f08 jesd204_rx: Add dynamic multi-link support
A multi-link is a link where multiple converter devices are connected to a
single logic device (FPGA). All links involved in a multi-link are synchronous
and established at the same time. For a RX link this means that the SYNC signal
needs to be propagated from the FPGA to each converter.

Dynamic multi-link support must allow to select to which converter devices on
the multi-link the SYNC signal is propagated too. This is useful when depending
on the usecase profile some converter devices are supposed to be disabled.

Add the cfg_links_disable[0x081] register for multi-link control and
propagate its value to the RX FSM.
2018-05-03 18:48:54 +03:00
Istvan Csomortani 09ff1f3a77 jesd204: Fix file names
All the file names must have the same name as its module. Change all the
files, which did not respect this rule.
Update all the make files and Tcl scripts.
2018-04-11 15:09:54 +03:00