4 Commits (3c49470e08b1749bf5b5ed54b19894857d037e06)

Author	SHA1	Message	Date
Istvan Csomortani	d3c6771ad6	axi_ad9371: Update dac_clk_ratio to 2 ... DAC sampling frequency is two times of the JESD204 core clock.	2017-05-10 11:36:07 +03:00
AndreiGrozav	a505d304af	Add up_dac_common missing connections	2016-10-12 13:20:26 +03:00
Istvan Csomortani	913eafed48	up_drp : Update the DRP interface to support Altera platforms	2016-09-21 15:00:45 +03:00
Rejeesh Kutty	b5b05bb9d1	axi_ad9371: added	2016-05-20 11:41:54 -04:00