Istvan Csomortani
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1c23cf4621
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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Istvan Csomortani
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7478777d8d
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axi_dacfifo: Match the ports with util_dacfifo
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2017-03-03 18:46:16 +02:00 |
|
Istvan Csomortani
|
3e596347fd
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axi_dacfifo: Delete unused wires
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2017-02-24 15:45:51 +02:00 |
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Istvan Csomortani
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f326c03ff3
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axi_dacfifo: Define constraint for bypass
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
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2017-02-24 12:35:42 +02:00 |
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Istvan Csomortani
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dfcd5214a0
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axi_dacfifo: axi_dvalid should come from dacfifo_rd module
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2017-02-24 12:28:46 +02:00 |
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Istvan Csomortani
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1fce57f6c3
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axi_dacfifo: Redesign the bypass functionality
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2017-02-23 17:32:31 +02:00 |
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Istvan Csomortani
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f10866e4c3
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axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
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2017-02-16 19:54:41 +02:00 |
|
Istvan Csomortani
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95a4ea20c8
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axi_dacfifo: Delete redundant parameter BYPASS_EN
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2017-02-16 19:53:44 +02:00 |
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Istvan Csomortani
|
3b0c1e02fc
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axi_dacfifo: Move IP to library/xilinx
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2016-09-15 11:38:16 +03:00 |