6 Commits (3b4aaec9260b074fd3d7869d4691295a0ce4dce0)

Author	SHA1	Message	Date
Istvan Csomortani	e3ea51ade3	avl_dacfifo: Refactor the fifo ... + Build both the read and write logic around an FSM + Consistent naming of registers and wires + Add support for burst lenghts higher than one, current burst lenght is 64 + Fix all the bugs, and make it work (first bring up with adrv9371x/a10soc)	2017-10-31 14:30:06 +00:00
Istvan Csomortani	7554887982	avl_dacfifo: Fix timing violation ... + Transfer avl_last_beats into dac clock domain + Update constraint file	2017-06-07 11:02:44 +01:00
Istvan Csomortani	cb8d6830f5	avl_dacfifo: Update constraints	2017-05-25 15:12:16 +03:00
Istvan Csomortani	77eafbcccd	avl_dacfifo: Update constarint file	2017-04-25 12:03:46 +03:00
Istvan Csomortani	4007df2094	avl_dacfifo: Update constraints	2017-04-21 17:25:46 +03:00
Istvan Csomortani	180a80493b	avl_dacfifo: Initial commit	2017-04-21 13:26:37 +03:00